t_FIFO_Clock_Domain_Synch.v

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上传日期:2008-07-10
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文件大小:3k
源码类别:VHDL/FPGA/Verilog
开发平台:VHDL
  1. module t_FIFO_Clock_Domain_Synch();
  2.     parameter stack_width=32;
  3.     parameter stack_height=8;
  4.     parameter stack_ptr_width=3;
  5.     defparam M1.stack_width=32;
  6.     defparam M1.stack_height=8;
  7.     defparam M1.stack_ptr_width=3;
  8.     
  9.     wire [stack_width-1:0] Data_out,Data_32_bit;
  10.     wire                   stack_full,stack_almost_full,stack_half_full;
  11.     wire                   stack_almost_empty,stack_empty;
  12.     wire                   write;
  13.     reg                    read_from_stack;
  14.     reg                    Data_in;
  15.     reg                    En;
  16.     reg                    clk_read,clk_write,rst;
  17.     wire [31:0]            stack0,stack1,stack2,stack3;
  18.     wire [31:0]            stack4,stack5,stack6,stack7;
  19.      //Probes of the stack
  20.     assign stack0=M1.stack[0];
  21.     assign stack1=M1.stack[1];
  22.     assign stack2=M1.stack[2];
  23.     assign stack3=M1.stack[3];
  24.     assign stack4=M1.stack[4];
  25.     assign stack5=M1.stack[5];
  26.     assign stack6=M1.stack[6];
  27.     assign stack7=M1.stack[7];
  28.     
  29.     //2-stage pipeline to compensate for latency at synchronizer
  30.     reg[stack_width-1:0] Data_1,Data_2;
  31.     always @(negedge clk_read)
  32.     if(rst)begin Data_2<=0;Data_1<=0;end
  33.     else begin Data_1=Data_32_bit;Data_2=Data_1;end
  34.   
  35.     Ser_Par_Conv_32 M00(Data_32_bit,write,Data_in,En,clk_write,rst);
  36.     write_synchronizer M0(write_synch,write,clk_read,rst);
  37.     FIFO_Buffer M1(Data_out,stack_full,stack_almost_full,stack_half_full,
  38.       stack_almost_empty,stack_empty,Data_2,write_synch,read_from_stack,
  39.       clk_read,rst);
  40.  
  41.        
  42.     initial #10000 $finish;
  43.     initial fork rst=1;#8 rst=0;join
  44.     initial begin clk_write=0;forever #4 clk_write=~clk_write;end //100MHZ
  45.     initial begin clk_read=0; forever #3 clk_read=~clk_read;end// 133MHz clock
  46.     initial fork #1 En=0;#48 En=1;#2534 En=0;#3944 En=1;join       
  47.     initial fork
  48.      #6 read_from_stack=0;
  49.      #2700 read_from_stack=1;#2706 read_from_stack=0;
  50.      #3980 read_from_stack=1;#3986 read_from_stack=0;
  51.      #6000 read_from_stack=1;#6006 read_from_stack=0;
  52.      #7776 read_from_stack=1;#7782 read_from_stack=0; //Overlaps write_synch
  53.     join
  54.    
  55.     //Serial data transitions are synchronized to the falling edge of clk_write
  56.     initial begin//Generate data and hold
  57.      #1 Data_in=0;
  58.      @(posedge En) Data_in=1; //wait for enable
  59.      @(posedge write)
  60.      repeat(6) begin
  61.      repeat(16)@(negedge clk_write)Data_in=0; 
  62.      repeat(16)@(negedge clk_write)Data_in=1; 
  63.      repeat(16)@(negedge clk_write)Data_in=1; 
  64.      repeat(16)@(negedge clk_write)Data_in=0;  
  65.      end
  66.    end    
  67.    
  68.    initial
  69.    //$monitor($time,"state=%b,next_state=%b,En=%b,write=%b,shift=%b,incr=%b",
  70.    //             M00.state,M00.next_state,En,M00.write,M00.shift,M00.incr);
  71.    //$monitor($time,"Data_in=%b,Data_out=%b",Data_in,Data_32_bit);
  72.    //$monitor($time,"stackfull=%b,Data_Input=%b,write_synch=%b,Data_2=%b",stack_full,Data_32_bit,write_synch,stack0);
  73.    $monitor($time,"stack0=%h,stack1=%h,stack2=%h,stack3=%h,Data_out=%h",stack0,stack1,stack2,stack3,Data_out);
  74. endmodule