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mt1389.h
资源名称：mt1389.rar [点击查看]
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上传日期：2019-12-22
资源大小：17k
文件大小：100k
源码类别：
DVD
开发平台：
C++ Builder
- /*************** MTK CONFIDENTIAL & COPYRIGHTED ****************/
- /*************** ****************/
- /*************** $Modtime:: 07/04/09 11:49a $ ****************/
- /*************** $Revision:: 7 $ ****************/
- /*************** ****************/
- /*************** Description : MT1389 register ****************/
- /*************** definition ****************/
- /*************** ****************/
- /*************** Company : MediaTek Inc. ****************/
- /*************** Programmer : Joseph Lin ****************/
- /**********************************************************************/
- #ifndef _H_MT1389_
- #define _H_MT1389_
- #define DEC_REG_START 0xF900 // Decoder register access
- #define BIM_REG_START 0xF800 // BUS INTERFACE MANAGER
- #define SRV_REG_START 0xFA00
- #define RW_BSTEST 0x0
- #define BSDEN (0x1 << 7)
- #define RW_PRITRL 0x3E // E6 only
- #define RW_FIFOCR 0x3F // E6 only
- #define RAMCC (1 << 5)
- #define RW_CMDQ 0x40 // Command Queue Control Register
- #define QSEL_2 (0 << 5) // Command queue depth 2
- #define QSEL_3 (1 << 5) // Command queue depth 3
- #define QSEL_4 (2 << 5) // Command queue depth 4
- #define QSEL_5 (3 << 5) // Command queue depth 5
- #define QSEL_6 (4 << 5) // Command queue depth 6
- #define QSEL_7 (5 << 5) // Command queue depth 7
- #define QSEL_8 (6 << 5) // Command queue depth 8
- #define QSEL_9 (7 << 5) // Command queue depth 9
- #define MBEN (1 << 4) // Burst mode enable
- #define CMDQ_EN (1 << 3) // Command queue enable
- #define TWR_0T (0 << 1) // Write recovery time 0 T
- #define TWR_1T (1 << 1) // Write recovery time 1 T
- #define TWR_2T (2 << 1) // Write recovery time 2 T
- #define TWR_3T (3 << 1) // Write recovery time 3 T
- #define RTW_0T (0 << 0) // No additional latency
- #define RTW_1T (1 << 0) // Additional 1T latency
- #define RW_RBCR0 0x41 // RAM buffer control 0
- #define TRAS_6T (0 << 6)
- #define TRAS_7T (1 << 6)
- #define TRAS_8T (2 << 6)
- #define TRAS_9T (3 << 6)
- #define TRP_1T (0 << 4)
- #define TRP_2T (1 << 4)
- #define TRP_3T (2 << 4)
- #define TRP_4T (3 << 4)
- #define TRCD_5T (0 << 2)
- #define TRCD_2T (1 << 2)
- #define TRCD_3T (2 << 2)
- #define TRCD_4T (3 << 2)
- #define MCASLT_1T (1 << 0) // CAS latancy 1T
- #define MCASLT_2T (2 << 0) // CAS latancy 2T
- #define MCASLT_3T (3 << 0) // CAS latancy 3T
- #define RW_RBCR1 0x42 // RAM buffer control 1
- #define DAW_4BK (1 << 7) // SDRAM 4 banks
- #define BWSEL_32 (1 << 6) // The external SDRAM bus width is 32-bits
- #define CBSEL_9 (1 << 5) // The external SDRAM column width is 9-bits (A0-A8)
- #define BREFEN (1 << 4) // Burst refresh before and after self refresh enable
- #define MBL_0 (0 << 1) // Minimum burst length 0
- #define MBL_1 (1 << 1) // Minimum burst length 1
- #define MBL_2 (2 << 1) // Minimum burst length 2
- #define MBL_3 (3 << 1) // Minimum burst length 3
- #define MBL_4 (4 << 1) // Minimum burst length 4
- #define MBL_5 (5 << 1) // Minimum burst length 5
- #define MBL_6 (6 << 1) // Minimum burst length 6
- #define MBL_7 (7 << 1) // Minimum burst length 7
- #define INITRG (1 << 0) // SDRAM initial trigger
- #define RW_RBCR2 0x43 // RAM buffer control 2
- #define MPDM (1 << 7) // SDRAM CKE power down mode
- #define MPDM_ON (0 << 7)
- #define MPDM_OFF (1 << 7)
- #define CLKDRV1_2 (0 << 3) // Driving strength of SDRAM clock
- #define CLKDRV1_4 (1 << 3)
- #define CLKDRV1_6 (2 << 3)
- #define CLKDRV1_8 (3 << 3)
- #define CLKDRV1_10 (4 << 3)
- #define CLKDRV1_12 (5 << 3)
- #define CLKDRV1_14 (6 << 3)
- #define CLKDRV1_16 (7 << 3)
- #define CLKDRV2_10 (8 << 3)
- #define CLKDRV2_12 (9 << 3)
- #define CLKDRV2_14 (10 << 3)
- #define CLKDRV2_16 (11 << 3)
- #define CLKDRV2_18 (12 << 3)
- #define CLKDRV2_20 (13 << 3)
- #define CLKDRV2_22 (14 << 3)
- #define CLKDRV2_24 (15 << 3)
- #define CCKDLY_00 (0 << 0) // The clock delay output 0.0ns
- #define CCKDLY_05 (1 << 0) // The clock delay output 0.5ns
- #define CCKDLY_10 (2 << 0) // The clock delay output 1.0ns
- #define CCKDLY_15 (3 << 0) // The clock delay output 1.5ns
- #define CCKDLY_20 (4 << 0) // The clock delay output 2.0ns
- #define CCKDLY_25 (5 << 0) // The clock delay output 2.5ns
- #define CCKDLY_30 (6 << 0) // The clock delay output 3.0ns
- #define CCKDLY_35 (7 << 0) // The clock delay output 3.5ns
- #define RW_REFC 0x44 // Refresh Period Counter
- #define REFC_MASK 0xFC
- #define REFT_1 (0 << 0) // Refresh once per Tref
- #define REFT_2 (1 << 0) // Refresh twice per Tref
- #define REFT_3 (2 << 0) // Refresh triple per Tref
- #define REFT_4 (3 << 0) //
- #define RW_MCTRL 0x45 // Main Channel Interface Control
- #define BSYEN (1 << 7) // CD buffering FIFO busy enable (to avoid overflow)
- #define C2EN (1 << 5) // CD-ROM C2PO data write enable
- #define DSPEN (1 << 4) // Auto enable CIRC decoding in CDDA
- #define SYDEN (1 << 3) // SYNC DECECTION ENABLE
- #define SYIEN (1 << 2) // SYNC INSERTION ENABLE
- #define DSCEN (1 << 1) // DISCRAMBLER ENABLE
- #define WRRQ (1 << 0) // DSP DATA WRITE REQUEST
- #define RW_MCIER 0x46 // Main Channel Interface INT Enable
- #define FIFOTH (1 << 7) // CD buffering FIFO request threshold
- #define SMTBIE (1 << 6) // 1:SMART TARGET FIND BLANK SECTOR ENABLE
- #define IDNMIEN (1 << 5) // 1:ID/PID AND TARGET COMPARE ENABLE
- #define DTSEN (1 << 4) // 1:Enable DTS CD detection
- #define NOEFMEN (1 << 3) // 1:NO EFM SIGINAL FOR ONE PERIOD
- #define IHCEN (1 << 2) // 1:ILLEGAL CDROM HEADER CHK ENABLE
- #define TNFIEN (1 << 1) // 1:TARGET NOT FOUND INT ENABLE
- #define TFIEN (1 << 0) // 1:TARGET FOUND INT ENABLE
- #define RD_MCSTA 0x47 // Main Channel Interface Status
- #define SMTBNK (1 << 7) // 1:BLANK SECTOR FOUND BY SMART TARGET
- #define IDNM (1 << 6) // 1:ID/PID NOT MATCH TARGET
- #define DTS16 (1 << 6) // 1: DTS CD 16 bit
- #define DTS14 (1 << 5) // 1: DTS CD 14 bit
- #define BCAEND (1 << 5) // BCA DECODE COMPLETE
- #define NOEFM (1 << 4) // 1:NO EFM SIGINAL
- #define OVERRUN (1 << 3) // 1:TARGET OVERRUN
- #define NOSYNC (1 << 2) // 1:SYNC NOT FOUND
- #define TNFI (1 << 1) // 1:TARGET NOT FOUND
- #define TFI (1 << 0) // 1:TARGET FOUND
- #define RW_SCTRL 0x48 // Subcode Control
- #define C2LAST (1 << 6) // C2PO request last enable
- #define CTEXT (1 << 5) // 1: CD TEXT ENABLE
- #define LMT64 (1 << 3) // 1: LIMIT 64
- #define SCWEN (1 << 2) // 1:SUBCODE WRITE ENABLE
- #define NOPQ (1 << 1) // 1:NO SUBCODE P AND Q
- #define SCEN (1 << 0) // 1:ENABL SUBCODE LOGIC
- #define RW_SCIER 0x49 // Subcode Interrupt Enable
- #define SBOKEN (1 << 4) // 1:SBOK INTERRUPT ENABLE
- #define QCLEAN (1 << 3) // 1:CLEAN SUB-Q CODE TARGET SEARCH
- #define MISSYEN (1 << 2) // Missing Q subchannel SYNC interrupt enable
- #define SBKEN (1 << 1) // Normal end of subcode block interrupt enable
- #define SILSYEN (1 << 0) // Illegal Q subchannel SYNC interrupt enable
- #define RD_SCSTA 0x4A // Subcode Status
- #define SBOK (1 << 3) // 1:SUB-Q CODE CRC STATUS OK
- #define MISSY (1 << 2) // 1:MISS SUBCODE SYNC
- #define SBKEND (1 << 1) // 1:NORMAL SUBCODE END
- #define SILSY (1 << 0) // 1:ILLEGAL SUBCODE SYNC
- #define RW_SEEKLMT 0x4B // CD Seek Limit
- #define RD_CDSC 0x4C // Seek Counter
- #define RW_RAMPC 0x4D // DRAM Pin Control Register 1
- #define CCKINV (1 << 7) // SDRAM clock inverting
- #define RAMDRV_2 (0 << 2) // DRAM interface pin driving strength
- #define RAMDRV_4 (1 << 2)
- #define RAMDRV_6 (2 << 2)
- #define RAMDRV_8 (3 << 2)
- #define RAMDRV_10 (6 << 2)
- #define RAMDRV_12 (7 << 2)
- #define RCPT (1 << 0)
- #define RW_RBCR3 0x4E // Buffer Memory Control Register 3
- #define DM_SREFEN (1 << 7) // DRAM Self Refresh
- #define APSEL_A10 (0 << 5) // SDRAM AP(auto precharge) pin select
- #define APSEL_A8 (1 << 5)
- #define APSEL_A9 (2 << 5)
- #define RW_RBCR4 0x4F // Buffer Memory Control Register 4
- #define DCKDLY_00 (0 << 5) // Data latch clock delay 0.0ns
- #define DCKDLY_05 (1 << 5) // Data latch clock delay 0.5ns
- #define DCKDLY_10 (2 << 5) // Data latch clock delay 1.0ns
- #define DCKDLY_15 (3 << 5) // Data latch clock delay 1.5ns
- #define DCKDLY_20 (4 << 5) // Data latch clock delay 2.0ns
- #define DCKDLY_25 (5 << 5) // Data latch clock delay 2.5ns
- #define DCKDLY_30 (6 << 5) // Data latch clock delay 3.0ns
- #define DCKDLY_35 (7 << 5) // Data latch clock delay 3.5ns
- #define DCKINV (1 << 4) // Data latch clock invert
- #define CCASLT_4T (0 << 2)
- #define CCASLT_1T (1 << 2)
- #define CCASLT_2T (2 << 2)
- #define CCASLT_3T (3 << 2)
- #define DATR (1 << 1) // SDRAM Auto-tune trigger
- #define DSTS (1 << 0) // Status bit for SDRAM auto-tuning
- #define RD_QDATA0 0x50 // SUB-Q CODE BYTE 0 REGISTER
- #define RD_QDATA1 0x51 // SUB-Q CODE BYTE 1 REGISTER
- #define RD_QDATA2 0x52 // SUB-Q CODE BYTE 2 REGISTER
- #define RD_QDATA3 0x53 // SUB-Q CODE BYTE 3 REGISTER
- #define RD_QDATA4 0x54 // SUB-Q CODE BYTE 4 REGISTER
- #define RD_QDATA5 0x55 // SUB-Q CODE BYTE 5 REGISTER
- #define RD_QDATA6 0x56 // SUB-Q CODE BYTE 6 REGISTER
- #define RD_QDATA7 0x57 // SUB-Q CODE BYTE 7 REGISTER
- #define RD_QDATA8 0x58 // SUB-Q CODE BYTE 8 REGISTER
- #define RD_QDATA9 0x59 // SUB-Q CODE BYTE 9 REGISTER
- #define RW_NBLK 0x5A // Number of blocks in buffer
- #define RW_NBLKH 0x5A // Number of blocks in buffer High
- #define RW_NBLKL 0x5B // Number of blocks in buffer Low
- #define RW_BBLK 0x5C // Buffering Block Index
- #define RW_BBLKH 0x5C // Buffering Block Index High
- #define RW_BBLKL 0x5D // Buffering Block Index Low
- #define RW_SBLK 0x5E // Subcode block Index
- #define RW_SBLKH 0x5E // Subcode block Index High
- #define RW_SBLKL 0x5F // Subcode block Index Low
- #define RW_TAR 0x60 // Target Sector
- #define RW_TARR 0x60 // Target Sector Reserved
- #define RW_TARH 0x61 // Target Sector High (Minute)
- #define RW_TARM 0x62 // Target Sector Medium (Second)
- #define RW_TARL 0x63 // Target Sector Low (Frame)
- #define RW_DBLK 0x64 // Decoding Block Index
- #define RW_DBLKH 0x64 // Decoding Block Index High
- #define RW_DBLKL 0x65 // Decoding Block Index Low
- #define RW_DCTRL0 0x66 // Decode Control Register 0
- #define ECCEN (1 << 7) // 1:ECC/EDC enable
- #define ACCEN (1 << 6) // 1:ECC acceleration enable
- #define DSECC (1 << 5) // 1:DVD Smart ECC
- #define QEN (1 << 5) // 1:CDROM Q error correction enable
- #define PEN (1 << 4) // 1:CDROM P error correction enable
- #define DBEDC (1 << 4) // 1:DVD Increase DBLK in ALL EDC O.K.
- #define MMASK (1 << 3) // 1:CDROM Mask Mode bits 7-5
- #define MF_MODE1 0x00 // 000 : MODE 1
- #define MF_XAFORM1 0x01 // 001 : MODE 2 FORM 1
- #define MF_XAFORM2 0x02 // 010 : MODE 2 FORM 2
- #define MF_MODE2 0x03 // 011 : MODE 2 AUTO FORM
- #define MF_AUTO 0x04 // 100 : AUTO MODE AUTO FORM
- #define MF_FMODEFORM 0x05 // 101 : FIXED MODE1 or MODE2 Form1
- #define MF_FMODEAFORM 0x06 // 110 : FIXED MODE, AUTO FORM
- #define RW_DCTRL1 0x67 // Decode Control Register 1
- #define RASEN (1 << 7) // auto stop buffering ctrl
- #define RAS (1 << 6) // auto stop buffering status
- #define LINK (1 << 5) // 1:Enable Auto Link
- #define METHOD1 (0 << 4) // Method 1
- #define METHOD2 (1 << 4) // Method 2
- #define DSKID (1 << 3) // 1:Skip DVD Sector ID check
- #define LKMODECLEAN (1 << 3) // 1:Enable Link Mode clean check
- #define RLIMIT01 (0x01) // RLIMIT = 1
- #define RLIMIT02 (0x02) // RLIMIT = 2
- #define RLIMIT03 (0x03) // RLIMIT = 3
- #define RLIMIT04 (0x04) // RLIMIT = 4
- #define RLIMIT05 (0x05) // RLIMIT = 5
- #define RLIMIT06 (0x06) // RLIMIT = 6
- #define RLIMIT07 (0x07) // RLIMIT = 7
- #define RLIMIT08 (0x08) // RLIMIT = 8
- #define RD_HDR0 0x68 // HEADER MINUTES (BCD)
- #define RD_HDR1 0x69 // HEADER SECOND (BCD)
- #define RD_HDR2 0x6A // HEADER FRAME (BCD)
- #define RD_HDR3 0x6B // HEADER MODE (BCD)
- #define RD_SHDR0 0x6C // SUBHEADER FILE NUMBER
- #define RD_SHDR1 0x6D // SUBHEADER CHANNEL NUMBER
- #define RD_SHDR2 0x6E // SUBHEADER SUBMODE NUMBER
- #define RD_SHDR3 0x6F // SUBHEADER CODING INFO
- #define RD_HDER 0x70 // CD Header/Subheader Error Flags
- #define RW_NSEC 0x71 // Number of Sectors to Decode
- #define RW_SRII 0x72 // Sector Ready Interrupt Interval
- #define RD_RSC 0x73 // Ready Sector Count
- #define RW_C2POL 0x74 // CD C2 Pointer Limit
- #define RD_C2POC 0x75 // CD C2 Pointer Count
- #define RW_DENEN 0x76 // Decode Error Notification Enable
- #define ILSYEN (1 << 7) // ILLSYNC OR SHORT BLK ERROR INT EN
- #define NOSYEN (1 << 6) // NO SYNC OR LONG BLK ERROR INT EN
- #define ADDREN (1 << 5) // CD Sector ADDRess MISMATCH INT ENable
- #define SNEN (1 << 5) // DVD SECTOR ID MISMATCH INT ENable
- #define MODEEN (1 << 4) // CD MODE ERROR INT ENable
- #define SIEN (1 << 4) // DVD SECTOR Information ERROR INT ENable
- #define FORMEN (1 << 3) // CD FORM ERRor INT ENable
- #define CPREN (1 << 3) // DVD CSS ERRor INT ENable
- #define EDCEN (1 << 2) // ECC FAILURE INT EN
- #define HDREN (1 << 1) // ERROR IN HEADER/SUBHEADER INT EN
- #define C2POEN (1 << 0) // C2PO COUNT EXCEEDS LIMIT INT EN
- #define UIDMEN (1 << 0) // User Expected ID Match
- #define RD_DESTA 0x77 // Decode Error Status
- #define ILSYER (1 << 7) // CD ILLSYNC OR SHORT BLK ERROR INT
- #define BLANKECC (1 << 7) // DVD-RAM BLANK ECC HAPPENING
- #define NOSYER (1 << 6) // CD NO SYNC OR LONG BLK ERROR INT
- #define BLANKSECTOR (1 << 6) // DVD-RAM BLANK SECTOR HAPPENING
- #define ADDRER (1 << 5) // CD Sector ADDRess MISMATCH
- #define SNER (1 << 5) // DVD SECTOR ID MISMATCH
- #define MODEER (1 << 4) // CD MODE ERROR
- #define SIER (1 << 4) // DVD SECTOR Information ERROR
- #define FORMER (1 << 3) // CD FORM ERRor
- #define CPRER (1 << 3) // DVD CSS ERRor
- #define EDCER (1 << 2) // ECC FAILURE INT
- #define HDRER (1 << 1) // CD HEADER/SUBHEADER Error
- #define DSEC (1 << 1) // DVD-RAM IRREPLACEMENT DEFECT LIST
- #define C2POER (1 << 0) // CD C2PO COUNT EXCEEDS LIMIT INT
- #define UIDM (1 << 0) // DVD USER EXPECTED ID MATCHED
- #define RW_DIEN 0x78 // Decode Interrupt Enable Register
- #define EMPIEN (1 << 7) // BC3 EMPTY INT ENABLE
- #define DCIEN (1 << 6) // DECODER OP COMPLETE INT ENABLE
- #define DEIEN (1 << 5) // DECODER ERROR INT ENABLE
- #define MCIEN (1 << 4) // MAIN CHANNEL INTERFACE INT ENABLE
- #define SCIEN (1 << 3) // SUBCODE INTERFACE INT ENABLE
- #define RISCIEN (1 << 2) // RISC INT ENABLE
- #define BUFIEN (1 << 1) // BUFFERING COUNTER INT ENABLE
- #define DMIEN (1 << 0) // DEFECT MANAGEMENT INT ENABLE
- #define RC_DISTA 0x79 // Decode Interrupt Status Register
- #define EMPI (1 << 7) // BC3 EMPTY INT
- #define DCI (1 << 6) // DECODER OP COMPLETE INT
- #define DEI (1 << 5) // DECODER ERROR INT
- #define MCI (1 << 4) // MAIN CHANNEL INTERFACE INT
- #define SCI (1 << 3) // SUBCODE INTERFACE INT
- #define RISCI (1 << 2) // RISC INT
- #define BUFI (1 << 1) // BUFFERING COUNTER INT
- #define DMI (1 << 0) // DEFECT MANAGEMENT INT
- #define RW_BC1 0x7A // Buffer Counter 1
- #define RW_BC1H 0x7A // Buffer Counter 1 High
- #define RW_BC1L 0x7B // Buffer Counter 1 Low
- #define RW_BC2 0x7C // Buffer Counter 2
- #define RW_BC2H 0x7C // Buffer Counter 2 High
- #define RW_BC2L 0x7D // Buffer Counter 2 Low
- #define RW_BCS 0x7E // Buffer Counter 1/2 Setting
- #define RW_BC1S 0x7E // Buffer Counter 1 Setting
- #define RW_BC2S 0x7F // Buffer Counter 2 Setting
- #define BC_DISABLE (1 << 7) // DISABLE BUFFERING COUNT
- #define BC_SUSPEND (1 << 6) // SUSPEND BUFFERING COUNT
- #define BC_NOINC 0x00 // 000:NO INCREMENT ON ANY EVENTS
- #define BC_BBLKINC 0x08 // 001:INCREMENT ON BBLK EVENTS
- #define BC_SBLKINC 0x10 // 010:INCREMENT ON SBLK EVENTS
- #define BC_DBLKINC 0x18 // 011:INCREMENT ON DBLK EVENTS
- #define BC_TBLKINC 0x20 // 100:INCREMENT ON TBLK EVENTS
- #define BC_ABLKINC 0x28 // 101:INCREMENT ON ABLK
- #define BC_NODEC 0x00 // 000:NO DECREMENT ON ANY EVENTS
- #define BC_BBLKDEC 0x01 // 001:DECREMENT ON BBLK EVENTS
- #define BC_SBLKDEC 0x02 // 010:DECREMENT ON SBLK EVENTS
- #define BC_DBLKDEC 0x03 // 011:DECREMENT ON DBLK EVENTS
- #define BC_TBLKDEC 0x04 // 100:DECREMENT ON TBLK EVENTS
- #define BC_ABLKDEC 0x05 // 101:DECREMENT ON ABLK
- #define RW_BCL 0x80 // Buffer Counter 1 Limit
- #define RW_BCLH 0x80 // Buffer Counter 1 Limit High
- #define RW_BCLL 0x81 // Buffer Counter 1 Limit Low
- #define RW_BCA 0x82 // Buffer Counter Adjustment
- #define RW_BCAH 0x82 // Buffer Counter Adjustment High
- #define RW_BCAL 0x83 // Buffer Counter Adjustment Low
- #define RW_TRIG 0x84 // Decoder Trigger Register
- #define READTRG (1 << 7) // READ OPERATION TRIG
- #define TARGETTRG (1 << 6) // READ IS TARGETED
- #define CLEANTRG (1 << 5) // CLEAN TARGET CHECK
- #define CDDATRG (1 << 4) // READ CDDA DATA
- #define REREADTRG (1 << 5) // REREAD DVD DATA
- #define REDECTRG (1 << 4) // REDECODE DVD DATA
- #define STOPRTRG (1 << 3) // STOP READ OPERATION TRIG
- #define DECTRG (1 << 2) // START DECODE OPERATION TRIG
- #define RESUMETRG (1 << 1) // RESUME DECODE OPERATION TRIG
- #define STOPDTRG (1 << 0) // STOP DECODE OPERATION TRIG
- #define RW_BMT 0x85
- #define CPBC (1 << 0) // Copy BC2 into BC1
- #define CPDBLK (1 << 1) // Copy DBLK into BBLK, SBLK
- #define RW_EID0 0x88 // Expected Decoded DVD SecID 0
- #define RW_EID1 0x89 // Expected Decoded DVD SecID 1
- #define RW_EID2 0x8A // Expected Decoded DVD SecID 2
- #define RW_EID3 0x8B // Expected Decoded DVD SecID 3
- #define AREA_DATA 0x00 // 00 Data area
- #define AREA_LEADIN 0x04 // 01 Lead-in area
- #define AREA_LEADOUT 0x08 // 10 Lead-out area
- #define AREA_MIDDLE 0x0C // 11 Middle area
- #define LAYER_0 0x00 // Layer 0
- #define LAYER_1 0x01 // Layer 1
- #define RW_EBLK 0x8C // DVD ECC Block Index
- #define RW_EBLKH 0x8C // DVD ECC Block Index High
- #define RW_EBLKL 0x8D // DVD ECC Block Index Low
- #define RW_SICE 0x8E // DVD Sector Info Check Enable
- #define FOREN (1 << 5) // 1:Sector format type check enable
- #define TRKEN (1 << 4) // 1:Tracking method check enable
- #define REFEN (1 << 3) // 1:Reflectivity check enable
- #define AREAEN (1 << 2) // 1:Area type check enable
- #define DATAEN (1 << 1) // 1:Data type check enable
- #define LAYEN (1 << 0) // 1:Layer number check enable
- #define RD_SICR 0x8F // DVD Sector Info Check Result
- #define FORR (1 << 5) // 1:Sector format type check result
- #define TRKR (1 << 4) // 1:Tracking method check result
- #define REFR (1 << 3) // 1:Reflectivity check result
- #define AREAR (1 << 2) // 1:Area type check result
- #define DATAR (1 << 1) // 1:Data type check result
- #define LAYR (1 << 0) // 1:Layer number check result
- #define RW_IDECC 0x90 // DVD Sector ID Err Correction Mode
- #define PIDUSEL (1 << 5) // PID Update Select
- #define SMTAR (1 << 4) // DVD Smart Target
- #define POPEN (1 << 3) // Enable PI's PO decoding
- #define IDCCHK (1 << 2) // DVD Sector ID Clean Check Enable
- #define IDECCON (1 << 1)
- #define IDERAON (1 << 0)
- #define RD_ECPR0 0x92 // Expected Decoded DVD Secotr CPR 0
- #define RD_ECPR1 0x93 // Expected Decoded DVD Secotr CPR 1
- #define RD_ECPR2 0x94 // Expected Decoded DVD Secotr CPR 2
- #define RD_ECPR3 0x95 // Expected Decoded DVD Secotr CPR 3
- #define RD_ECPR4 0x96 // Expected Decoded DVD Secotr CPR 4
- #define RD_ECPR5 0x97 // Expected Decoded DVD Secotr CPR 5
- #define RD_DID0 0x98 // Decoded DVD Sector ID 0
- #define RD_DID1 0x99 // Decoded DVD Sector ID 1
- #define RD_DID2 0x9A // Decoded DVD Sector ID 2
- #define RD_DID3 0x9B // Decoded DVD Sector ID 3
- #define RD_IID0 0x9C // Incoming DVD Sector ID 0
- #define RD_IID1 0x9D // Incoming DVD Sector ID 1
- #define RD_IID2 0x9E // Incoming DVD Sector ID 2
- #define RD_IID3 0x9F // Incoming DVD Sector ID 3
- #define RW_BC3 0xA8 // Buffer Counter 3
- #define RW_BC3R 0xA8 // Buffer Counter 3 Reserved
- #define RW_BC3H 0xA9 // Buffer Counter 3 High
- #define RW_BC3M 0xAA // Buffer Counter 3 Middle
- #define RW_BC3L 0xAB // Buffer Counter 3 Low
- #define RW_BC3S 0xAC // Buffer Counter 3 Setting
- #define RW_BPC 0xC2
- #define RUN (1 << 0) // 1: Run Batch Register Programming
- #define RW_BPAR 0xC4 // Batch Program Reserved Address
- #define RW_BPAH 0xC5 // Batch Program High Address
- #define RW_BPAM 0xC6 // Batch Program Middle Address
- #define RW_BPAL 0xC7 // Batch Program Low Address
- #define RW_RXD 0xD6 // RS232 RECEIVE PORT
- #define RW_TXD 0xD6 // RS232 TRANSMIT PORT
- #define RD_RSFLG 0xD7 // RS232 FLAG REGISTER
- #define RSCEE (1 << 7) // Check End Error
- #define RSRO (1 << 6) // RECEIVE OVERFLOW
- #define RSTO (1 << 5) // TRANSMIT OVERFLOW
- #define RSRBF (1 << 4) // RECEIVE BUF FULL
- #define RSTBF (1 << 3) // TRANSMIT BUF FULL
- #define RW_DITA 0xE0 // Defect Info Table Address
- #define RW_TLSN 0xE1 // Target Logic Sector Number
- #define RW_ULSN 0xE2 // User-Specific Logic Sector Number
- #define RW_ZBLSN 0xE3 // Zone Boundary LSN
- #define RW_DMO 0xE4 // Defect Manager Operation Register
- #define DMO_DMBSY (1 << 7) // Defect Manager Busy
- #define DMO_RSDL (1 << 6) // Replacement SDL
- #define DMO_IRSDL (1 << 5) // Irreplacement SDL
- #define DMO_PDL (1 << 4) // PDL Defect
- #define RSTRWP (1 << 2) // Reset DM register pointers
- #define TRANS (1 << 1) // Translates TLSN to PSN in Target
- #define INITDIT (1 << 0) // Initialize Zone PDL pointer in DIT
- #define RW_DMC 0xE5 // Defect Manager Control Register
- #define SEC_STM_EN (1 << 5) // Sector Streaming Enable
- #define DMUPDN (1 << 4) // Defect Manager Power Down
- #define ZBAS (1 << 3) // Auto Stop at Zone Boundary
- #define STREAM (1 << 2) // Streaming Mode
- #define AUTOLR (1 << 1) // Auto Linear Replacement
- #define AUTOSLP (1 << 0) // Auto Slipping
- #define RW_DMIER 0xE6 // Defect Manager Interrupt Enable
- #define ULSNREN (1 << 6) // User-Specific LSN Reach
- #define ZBREN (1 << 5) // Zone Boundary Reach
- #define RSDLDEN (1 << 4) // Replacement SDL
- #define RBEEN (1 << 3) // Replacement Block End
- #define IRSDLDEN (1 << 2) // Irreplacement SDL
- #define IRSDLEEN (1 << 1) // Irreplacement SDL Block End
- #define PDLDEN (1 << 0) // PDL Reach
- #define RC_DMSTA 0xE7 // Defect Manager Interrupt Status
- #define ULSNR (1 << 6) // User-Specific LSN Reach
- #define ZBR (1 << 5) // Zone Boundary Reach
- #define RSDLD (1 << 4) // Replacement SDL
- #define RBE (1 << 3) // Replacement Block End
- #define IRSDLD (1 << 2) // Irreplacement SDL
- #define IRSDLE (1 << 1) // Irreplacement SDL Block End
- #define PDLD (1 << 0) // PDL Reach
- #define RW_HIM 0xE8
- #define IMODE_IDE 0x00 // IDE INTERFACE
- #define IMODE_PARAL 0x01 // Parallel AV
- #define IMODE_SER1 0x02 // Serial Port 1
- #define IMODE_SER2 0x03 // Serail Port 2
- #define IMODE_DUAL 0x04 // Dual Port
- #define RW_BPX 0xEA // Batch Program Parameter X
- #define RW_BPY 0xEB // Batch Program Parameter Y
- #define RD_PIDSTA 0xF0 // PID Status Register
- #define PID34OK 0x20 // PID34 O.K.
- #define PID34CLN 0x10 // PID34 Clean Flag
- #define PID12OK 0x02 // PID12 O.K.
- #define PID12CLN 0x01 // PID12 Clean Flag
- #define RW_C1C2R 0xF0 // CIRC/RSPC Error Flag
- #define RW_TXCTRL 0xF1 // DVD_RAM Sector Transfer Control
- #define STMINTREN (1 << 7) // Decoding Error Int in Stream Mode
- #define BESSITEN (1 << 6) // Blank ECC decoding error interrupt
- #define BNKINTREN (1 << 5) // Decoding error int if blank is detected
- #define DFTINTREN (1 << 4) // Decoding error int in inreplaceable SDL defect
- #define BNKLEV (1 << 3) // Blank level for a sector
- #define BECCTXSEL (1 << 2) // Blank ECC transfer mode select
- #define BNKTXSEL (1 << 1) // Blank Sector Transfer Mode
- #define DFTTXSEL (1 << 0) // Defect Sector Transfer Mode Select
- #define RW_BCARC 0xF2 // BCA Rebuffer Control Register
- #define BCASEL (1 << 4) // BCA Select
- #define BCARTIME1 0x02 // BCA Rebuffer Count
- #define BCARTIME2 0x04 // BCA Rebuffer Count
- #define BCARTIME3 0x06 // BCA Rebuffer Count
- #define BCARTIME4 0x08 // BCA Rebuffer Count
- #define BCARTIME5 0x0A // BCA Rebuffer Count
- #define BCARTIME6 0x0C // BCA Rebuffer Count
- #define BCARTIME7 0x0E // BCA Rebuffer Count
- #define BCARTIME8 0x00 // BCA Rebuffer Count
- #define BCAREB 0x01 // BCA Rebuufer Enable
- #define RD_BCASTA 0xF3 // BCA Status Register
- #define BCAOK (1 << 4) // BCA OK Status
- #define BCAN 0x0F // BCA N rows value
- #define RW_CIRCCTL 0xF4 // CIRC Control Register
- #define PIECCALIGN (1 << 7) // PI Error Count Aligned ECC
- #define CDERRCNT_01 (0 << 6) // 1 Sector Error Cal Interval
- #define CDERRCNT_75 (1 << 6) // 75 Sector Error Cal Interval
- #define DVDERRCNT_01 (0 << 6) // 1 ECC Error Cal Interval
- #define DVDERRCNT_42 (1 << 6) // 42 Sector Error Cal Interval
- #define PI_FRMERR (0 << 5) // PI frame error number
- #define PI_ERROR (1 << 5) // PI error number
- #define C1C2_NOSFRMERR (0 << 5) // C1/C2 no solution frame
- #define C1C2_FRMERR (1 << 5) // C1/C2 frame error number
- #define CDROMCIRC1 (0x10) // CDROM Strategy 1
- #define CDROMCIRC2 (0x14) // CDROM Strategy 2
- #define CDDACIRC1 (0x18) // CDDA Strategy 1
- #define CDDACIRC2 (0x1C) // CDDA Strategy 2
- #define CDDANEWCIRC2 (0x08) // CDDA new Strategy 2
- #define DISC2 (1 << 1) // Disable C2 correction
- #define DISC1 (1 << 0) // Disable C1 correction
- #define RW_REGCTRL 0xF5 // Monitor Control Register
- #define UEIDRWLOW 0x00 // Write/Read Low Byte
- #define UEIDRWMID 0x10 // Write/Read Middle Byte
- #define UEIDRWHIGH 0x20 // Write/Read High Byte
- #define CD_C1C2 0x00 // CD C1/C2 Error
- #define DVD_PIPO 0x01 // DVD PI/PO Error
- #define DVD_PIPO_FRM 0x02 // DVD PI/PO Frame Error
- #define RW_UEID 0xF6 // User Expected Decoded ID
- #define RD_DECMONSTA0 0xF7 // Decoder Monitor Status Reg
- #define RD_DECMONSTA1 0xF8 // Decoder Monitor Status Reg
- #define RD_DECMONSTA2 0xF9 // Decoder Monitor Status Reg
- #define RD_DECMONSTA3 0xFA // Decoder Monitor Status Reg
- #define RW_RBFSEC 0xFB // DVD-RAM rebuffer sector index register
- #define RW_ILSYNC 0xFC // illegal SYNC detection status
- #define ILSYNC (1 << 3) // illegal SYNC detected
- #define RW_ISMASK 0xFD // illegal SYNC interrupt mask
- #define ISMASK (1 << 7) // illegal SYNC interrupt mask
- #define RW_REGCTRL1 0xFE // Register monitor control register
- #define NCSOP_6 (0 << 6) // Continuously no-solution number is 6
- #define NCSOP_8 (1 << 6) // Continuously no-solution number is 8
- #define NCSOP_10 (2 << 6) // Continuously no-solution number is 10
- #define NCSOP_12 (3 << 6) // Continuously no-solution number is 12
- #define NANOP_1 (0 << 4) // The postponed number is 1
- #define NANOP_2 (1 << 4) // The postponed number is 2
- #define NANOP_3 (2 << 4) // The postponed number is 3
- #define NANOP_4 (3 << 4) // The postponed number is 4
- #define NEWECCOP (1 << 3) // ehold will be set
- #define RSPOWER (1 << 2) // rs_engine is always on
- #define DECMCLK (1 << 1) // DRAM clock is on
- #define DSPMCLK (1 << 0) // DRAM clcck is on
- #define RW_REGCTRL2 0xFF // Register monitor control register
- #define C1ESETEN (1 << 7) // Enable C1 automatically set erasure
- #define NOSOLADD (1 << 6) // Enable postponing C1 no-solution length
- //////////////////////////////////////////////////////
- // definition of decoder Register
- #define CDROM_AUTO_CIRC CDROMCIRC1
- #define CDROMXA_AUTO_CIRC CDROMCIRC1
- #define CDDA_AUTO_CIRC CDDANEWCIRC2
- // definition of servo Register
- #ifdef MT1389LK_DIGITAL_SERVO
- // For 1389L/K, DPUCmd 35[7:6] = 11, by Jethro
- #define CDROM_ENA_CIRC 0xEA
- #define CDDA_ENA_CIRC 0xDA
- #define CDDA_DIS_CIRC 0xC8
- #else
- #define CDROM_ENA_CIRC 0x2A
- #define CDDA_ENA_CIRC 0x1A
- #define CDDA_DIS_CIRC 0x08
- #endif
- #define DVD_AUTO_RSPC 0x22
- #define DVDRAM_AUTO_RSPC 0xE6
- // the Despike register for MT1379 was moved to 0x48,
- // and will be initialed by SERVO
- // SDATA data interpolation control
- #define ITMD_1_C2PO 0x00
- #define ITMD_3_C2PO 0x10
- // Interpolation
- #define ENA_INPT (0 << 3)
- #define DIS_INPT (1 << 3)
- // Path Select
- #define CDROM_MODE (1 << 2)
- #define CDDA_MODE (0 << 2)
- // Avoid Left/Right Channel Shift
- #define ITSEL (1 << 1)
- #define CDROM_PATH (CDROM_MODE)
- #define CDDA_DIS_INTP (CDDA_MODE + DIS_INPT)
- #define CDDA_ENA_INTP (CDDA_MODE + ENA_INPT + ITSEL)
- //////////////////////////////////////////////////////
- // BIM registers definition
- #define BIM_RISCSSH 0x40
- #define BIM_RISCSSL 0x41
- #define BIM_RISCS3 0x42
- #define BIM_RISCS2 0x43
- #define BIM_RISCS1 0x44
- #define BIM_RISCS0 0x45
- #define BIM_DBGC 0x48
- #define RSTOP (1 << 0) // RISC stop
- #define BIM_DBGS 0x49
- #define BIM_CHK1H 0x4A
- #define BIM_CHK1L 0x4B
- #define BIM_CHK2H 0x4C
- #define BIM_CHK2L 0x4D
- #define BIM_CHK1A 0x4E
- #define BIM_CHK2A 0x4F
- #define BIM_SIFSel 0x50
- #define Device_Addr 0x00
- #define Word_Addr 0x01
- #define W_Data 0x02
- #define R_Data 0x03
- #ifndef MT1389_REV_P
- #define SIFCfg 0x10
- #else
- #define SIFCFG 0x15
- #define SIFCLK_CNT 0x18
- #define SIFCTRL 0x19
- #define SIFACK 0x1A
- #endif
- #define BIM_SIFData 0x51
- #define SIFAACK (1 << 2)
- #define SIFCKSEL_30K 0x00
- #define SIFCKSEL_120K 0x01
- #define SIFCKSEL_480K 0x02
- #define BIM_SCTRL 0x52
- #define SIFEN (1 << 0)
- #define SIFBIDA (1 << 1)
- #define SIFTRI (1 << 2)
- #define SIFWR (1 << 3)
- #if (defined(MT1389_REV_K))
- #define SIFCURAR (1 << 4)
- #define SIFHD1T (1 << 5)
- #define BIM_SIFIC 0x53
- #define SACDCLR (1 << 6)
- #define BIM_SIFINT 0x54
- #define SIFMI (1 << 0)
- #define VFDI (1 << 1)
- #define SIFS0I (1 << 2)
- #define SIFS1I (1 << 3)
- #define EXTI (1 << 4)
- #define SDHOS (1 << 5)
- #define PSPDET (1 << 6) //G.T??
- #endif
- #define BIM_STAT 0x60
- #define ICEM (1 << 7) // ICE MODE
- #define E373 (1 << 6) // 1 external, 0 internal
- #define MBSY (1 << 5) // DRAM busy
- #define HPIN (1 << 4) // 1: 256 pins package
- #define EMU (1 << 1) // 1: emulation SRAM avaiable
- #define RICE (1 << 0) // RICE in ICE mode
- #define BIM_MARH 0x61 // DRAM write port address High
- #define BIM_MARM 0x62 // DRAM write port address Mid
- #define BIM_MARL 0x63 // DRAM write port address Low
- #define BIM_MDAT 0x64 // DRAM write Data port
- #define BIM_FRST 0x65 // Firmware Reset
- #define CTRST (1 << 3) // Counter reset
- #define RPOR (1 << 2) // RISC power-on reset
- #define RRST (1 << 1) // RISC firmware reset
- #define FRST (1 << 0) // 8032 firmware reset
- #define BIM_PCTL1 0x66 // Pin Control 1 Register
- #if (!defined(MT1389_REV_P) && !defined(MT1389_REV_K))
- #define OSCEN (1 << 7) // Oscillator Enable
- #else
- #define A22EN (1 << 7) // A22 Enable
- #endif
- #define A21EN (1 << 6) // A20 Enable
- #define A20EN (1 << 5) // A20 Enable
- #if defined(MT1389_REV_K) //G.T1225:BIM Rechecking: Here is different from 89L porting.
- #define IOFLG (1 << 4) // Servo Flag Mode
- #define A19LOCK (1 << 3)
- #define A18LOCK (1 << 2)
- #define A17LOCK (1 << 1)
- #define A16LOCK (1 << 0)
- #else
- #define A19EN (1 << 4) // A19 Enable
- #define IOFLG (1 << 3) // Servo Flag Mode
- #define A18LOCK (1 << 2)
- #define A17LOCK (1 << 1)
- #define A16LOCK (1 << 0)
- #endif
- #ifdef BANK_NO
- #if (BANK_NO > 4) // use 8 banks
- #define ADDR_LOCK (A16LOCK | A17LOCK | A18LOCK)
- #else
- #define ADDR_LOCK (A16LOCK | A17LOCK)
- #endif
- #endif
- #define BIM_PCTL2 0x67 // Pin Control 2 Register
- #define EXTCS (1 << 7) // External Chip-Select Enable
- #define F4MX2 (1 << 6) // Use two 4M Flash
- #define XL54M (1 << 5) // Use external 54M clock
- #define LEDEN (1 << 4) // LED Enable
- #define CS_EN (1 << 3) // Flash CS Enable
- #if (defined(MT1389_REV_L) || defined(MT1389_REV_K))
- #define RS232P2 (1 << 2)
- #define CKM (1 << 1) // Clock Monitor Enable
- #define DSPT (1 << 0) //
- #else
- #define CKM (1 << 2) // Clock Monitor Enable
- #define DSPT (1 << 1) //
- #define W_EN (1 << 0) // Flash WR Enable
- #endif
- #define BIM_IOENH 0x68
- #define BIM_IOENM 0x69
- #define BIM_IOENL 0x6A
- #define BIM_IODRH 0x68
- #define BIM_IODRM 0x69
- #define BIM_IODRL 0x6A
- #define BIM_IODOH 0x6B
- #define BIM_IODOM 0x6C
- #define BIM_IODOL 0x6D
- #define BIM_IODIH 0x6E
- #define BIM_IODIM 0x6F
- #define BIM_IODIL 0x70
- // BIM_IOENH,BIM_IODOH,BIM_IODIH
- #define IOH_VSYN (1 << 0)
- #define IOH_YUV7 (1 << 3)
- #define IOH_SPBCK (1 << 4)
- #define IOH_SPLRCK (1 << 5)
- #define IOH_SPDATA (1 << 6)
- #define IOH_SPMCLK (1 << 7)
- // BIM_IOENM,BIM_IODOM,BIM_IODIM
- #define IOM_A16 (1 << 0)
- #define IOM_A17 (1 << 1)
- #define IOM_A18 (1 << 2)
- #define IOM_A19 (1 << 3)
- #define IOM_A20 (1 << 4)
- #define IOM_A21 (1 << 5)
- #define IOM_BLANK (1 << 6)
- #define IOM_HSYN (1 << 7)
- // BIM_IOENL,BIM_IODOL,BIM_IODIL
- #ifdef FLASH_SZ
- #if (FLASH_SZ == 4)
- #define IOM_BMASK (IOM_A16 | IOM_A17 | IOM_A18 | IOM_A19 | IOM_A20 | IOM_A21)
- #elif (FLASH_SZ == 2)
- #define IOM_BMASK (IOM_A16 | IOM_A17 | IOM_A18 | IOM_A19 | IOM_A20)
- #else /* 1M byte flash */
- #define IOM_BMASK (IOM_A16 | IOM_A17 | IOM_A18 | IOM_A19)
- #endif
- #endif
- #define IOH_VSYN (1 << 0)
- #define IOH_IOWR (1 << 1)
- #define IOH_IOCS (1 << 2)
- #define IOH_XTALI (1 << 3)
- #define IOH_SPBCK (1 << 4)
- #define IOH_SPLRCK (1 << 5)
- #define IOH_SPDATA (1 << 6)
- #define IOH_SPMCLK (1 << 7)
- #define BIM_MAP 0x71 // Map rom in ICE mode
- #define VRAM2 (2 << 1) // enable virtual SRAM 2
- #define VRAM (1 << 1) // enable virtual SRAM
- #define MAPROM (1 << 0)
- #if defined(MT1389_REV_K)
- #define HI_GPR_SEL (1 << 3) //Enable acess to additional 128 bytes GPR.
- #define GPRCK (1 << 2) //General purpose ram clock select
- #endif
- #define BIM_DUAL 0x72
- #define CPU_HALF_EN (1 << 3)
- #define IN2K (1 << 2)
- #define DUALEN (1 << 0)
- #define BIM_CFLA 0x73
- #define CFLA (1 << 0)
- #define BIM_ADDREN 0x74
- #define ROMEN (1 << 7)
- #define FAEN (1 << 6)
- #define FNEN (1 << 5)
- #define DACEN (1 << 4)
- #define DANEN (1 << 3)
- #define DBCEN (1 << 2)
- #define DBNEN (1 << 1)
- #define IOEN (1 << 0)
- #define BIM_FCBA 0x75 // Flash Cache Addr
- #define BIM_FNBA 0x76 // Flash Non-Cache Addr
- #define BIM_ACBA 0x77 // DRAM A Cache Addr
- #define BIM_ANBA 0x78 // DRAM A Non-Cache Addr
- #define BIM_BCBA 0x79 // DRAM B Cache Addr
- #define BIM_BNBA 0x7A // DRAM B Non-Cache Addr
- #define BIM_IOBA 0x7B // IO Addr
- #define BIM_DPAH 0x7C // DRAM Partition Register
- #define BIM_DPAM 0x7D
- #define BIM_DPAL 0x7E
- #define BIM_CFG 0x7F // Configuration Register
- #define BCDEN (1 << 7) // Binary to BCD enable
- #define FASTM (1 << 6) // 8032 Fast mode
- #define DVDPRW (1 << 4) // DVD+RW 4.7G mode
- #define DVDRAMVER2 (1 << 3) // DVD-RAM version 2 mode
- #define DVDRAMVER1 (0 << 3) // DVD-RAM version 1 mode
- #define DVDRAM 0x06 // DVD-RAM mode
- #define DVDMODE (1 << 1) // DVD mode
- #define CDMODE (1 << 0) // CD mode
- #ifdef IR_USE_HW
- #define BIM_IR_CNT 0x80 // IR bit count
- #define BIM_IR_VAL 0x81 // IR 1st/2nd/decoded value
- #else
- #define BIM_IRL 0x81 // IR counter low
- #define BIM_IRH 0x80 // IR counter high
- #endif
- #define BIM_IR_CFGH 0x82 // IR configuration high register
- #define IR_END_7 0x00 // If sampling counter 7, delcare IR end pattern
- #define IR_END_15 0x40 // If sampling counter 15, delcare IR end pattern
- #define IR_END_23 0x80 // If sampling counter 23, delcare IR end pattern
- #define IR_END_31 0xC0 // If sampling counter 31, delcare IR end pattern
- #define IR_IGSYN (1 << 5) // Ignore IR first synchronization bit
- #define IR_ORDI (1 << 4) // The decoded IR pulse is bit reversed
- #define IR_RC5 (1 << 2) // IR RC5 format is used
- #define IR_INV (1 << 1) // IR pulse inverse before decode
- #define IR_HW (1 << 0) // IR H/W sampling counter
- #define BIM_IR_CFGL 0x83 // IR configuration low register
- #define BIM_RISCIEN 0x84 // RISC Interrupt enable register
- #define IRIEN (1 << 7) // IR interrupt enable
- #define EEVTIEN (1 << 6) // RISC event interrupt enable
- #define SIFIE (1 << 5) // Serial interface interrupt enable
- #define RSIEN (1 << 4) // RS232 interrupt enable
- #define HZIEN (1 << 3) // HTL Zero zero interrupt enable
- #define POKIEN (1 << 2) // Parser OK interrupt enable
- #define SMBIEN (1 << 1) // Share Memory B interrupt enable
- #define CMDIEN (1 << 0) // Command interrupt enable
- #define BIM_RISCI 0x85 // RISC Interrupt status register
- #define IRI (1 << 7) // IR interrupt
- #define EEVTI (1 << 6) // RISC event interrupt
- #define SIFI (1 << 5) // Serial interface interrupt
- #define RSI (1 << 4) // RS232 interrupt
- #define HZI (1 << 3) // HTL Zero zero interrupt
- #define POKI (1 << 2) // Parser OK interrupt
- #define SMBI (1 << 1) // Share Memory B interrupt
- #define CMDI (1 << 0) // Command interrupt
- #define BIM_ASSI 0x86 // Assert RISC Interrupt Register
- #define AOSD (1 << 3) // Assert OSD to RISC
- #define ASTA (1 << 2) // Assert Status to RISC
- #define ASA (1 << 1) // Assert Share Memory A to RISC
- #define AIRC (1 << 0) // Assert IR Command to RISC
- #define BIM_TRB0 0x87 // TASK Register B
- #define BIM_TRB1 0x88
- #define BIM_TRB2 0x89
- #define BIM_TRB3 0x8A
- #define BIM_TRB4 0x8B
- #define BIM_TRB5 0x8C
- #define BIM_TRB6 0x8D
- #define BIM_TRB7 0x8E
- #define BIM_TRB8 0x8F
- #define BIM_TRB9 0x90
- #define BIM_TRB10 0x91
- #define BIM_TRB11 0x92
- #define BIM_TRB12 0x93
- #define BIM_TRB13 0x94
- #define BIM_TRB14 0x95
- #define BIM_TRB15 0x96
- #define BIM_TRA0 0x97 // Task Register A
- #define BIM_TRA1 0x98
- #define BIM_TRA2 0x99
- #define BIM_TRA3 0x9A
- #define BIM_TRA4 0x9B
- #define BIM_TRA5 0x9C
- #define BIM_TRA6 0x9D
- #define BIM_TRA7 0x9E
- #define BIM_TRA8 0x9F
- #define BIM_TRA9 0xA0
- #define BIM_TRA10 0xA1
- #define BIM_TRA11 0xA2
- #define BIM_RISCBF 0xA3 // RISC Bus Clock Control Register
- #define BF_CLK_MASK 0x1F
- #define BF_27M 0x18 // Use 27MHz as bus clock
- #define BF_D2 0x00 // RISC clock divided by 2
- #define BF_D4 0x01 // RISC clock divided by 4
- #define BF_D6 0x02 // RISC clock divided by 6
- #define BF_D8 0x03 // RISC clock divided by 8
- #define BF_D10 0x04 // RISC clock divided by 10
- #define BF_D12 0x05 // RISC clock divided by 12
- #define BF_D14 0x06 // RISC clock divided by 14
- #define BF_D16 0x07 // RISC clock divided by 16
- #define RISCCD4 0x01 // RISC clock divided by 2
- #define BIM_CRBSY 0xA4 // Clear Busy Register
- #define CRCB (1 << 0) // clear command busy
- #define CRSMB (1 << 1) // clear share memory busy
- #define CRIR (1 << 2) // clear IR
- #define CREVT (1 << 3) // clear error event
- #define BIM_FLCTL 0xA5 // Flow Control Register
- #define PSTART (1 << 0) // start transfer
- #define BIM_TBLK 0xA6 // Transfer Block Register
- #define BIM_TBLKH 0xA6
- #define BIM_TBLKL 0xA7
- #define BIM_TLBAR 0xA8 // Transfer LBA Register
- #define BIM_TLBAH 0xA8
- #define BIM_TLBAM 0xA9
- #define BIM_TLBAL 0xAA
- #define BIM_HTL 0xAB // Transfer Length Register
- #define BIM_HTLH 0xAB
- #define BIM_HTLM 0xAC
- #define BIM_HTLL 0xAD
- #define BIM_WKUP 0xAE // Wakeup Control Register
- #define WKCNT_200US 0x00 // pulse width 200us
- #define WKCNT_1600US 0x01 // pulse width 1.6ms
- #define WKCNT_13MS 0x02 // pulse width 13ms
- #define WKCNT_26MS 0x03 // pulse width 26ms
- #define WINTE (1 << 2) // Wakeup by Interrupt
- #define WIRE (1 << 3) // Wakeup by IR
- #define WITST (1 << 6) // Interrupt Wakeup Status
- #define WIRST (1 << 7) // IR Wakeup Status
- #define BIM_DRVC 0xAF // Drive Control Register
- #define CYDRV (1 << 6) // Crystal Pad Driving Strength
- #define FDRV_2MA 0x00 // 8032 fast signal driving 2mA
- #define FDRV_4MA 0x08 // 8032 fast signal driving 4mA
- #define FDRV_6MA 0x10 // 8032 fast signal driving 6mA
- #define FDRV_8MA 0x18 // 8032 fast signal driving 8mA
- #define FDRV_10MA 0x20 // 8032 fast signal driving 10mA
- #define FDRV_12MA 0x28 // 8032 fast signal driving 12mA
- #define FDRV_14MA 0x30 // 8032 fast signal driving 14mA
- #define FDRV_16MA 0x38 // 8032 fast signal driving 16mA
- #define SDRV_2MA 0x00 // 8032 slow signal driving 2mA
- #define SDRV_4MA 0x01 // 8032 slow signal driving 4mA
- #define SDRV_6MA 0x02 // 8032 slow signal driving 6mA
- #define SDRV_8MA 0x03 // 8032 slow signal driving 8mA
- #define SDRV_10MA 0x04 // 8032 slow signal driving 10mA
- #define SDRV_12MA 0x05 // 8032 slow signal driving 12mA
- #define SDRV_14MA 0x06 // 8032 slow signal driving 14mA
- #define SDRV_16MA 0x07 // 8032 slow signal driving 16mA
- #if defined(MT1389_REV_P) || defined(MT1389_REV_L) || defined(MT1389_REV_K)
- #define BIM_CAL 0xB0 // APLL Control 0 Register
- #define APLL_PD (1 << 0) // APLL Power Down
- #define APLL_PM_SEL (1<< 1)
- #define APLL_CALE (1 << 2) // APLL calibration enable
- #define APLL_BD_MASK 0xF8
- #define BIM_APLLC1 0xB1 // APLL Control 1 Register
- #define APLL_IACGB (2<<4) //IACGB set 2
- #define DAC_MUTE_DIV (3<<6)
- #define BIM_APLLC2 0xB2 // APLL Control 2 Register
- #define APLL_DAC_RST (1<<4)
- #define APLL_MUTE_RST (1<<5)
- #define APLL_A2K2_RST (1<<6)
- #define APLL_AMAN_RST (1<<7)
- #define APLL_POR_B (1<<3) //when Calibration set it to be 0
- #define APLL_IPDO (3<<0)
- #define BIM_ADAC_LPF_DIV 0xB3 //Internal Audio DAC clock divider
- #define BIM_ADAC_MOD_DIV 0xB4 //Internal Audio DAC clock divider
- #define BIM_AN_L 0xB5 // APLL Divide-N[0:7] Register
- #else
- #define BIM_APLLC1 0xB0 // APLL Control 1 Register
- #define APLL_PD (1 << 0) // APLL Power Down
- #define APLL_BD_MASK 0x3E
- #define BIM_APLLC2 0xB1 // APLL Control 2 Register
- #define BIM_APLLC3 0xB2 // APLL Control 3 Register
- #define APLLC3_SETTING (0x01)
- #define BIM_CAL 0xB3 // APLL Calibration Register
- #define APLL_CALT (1 << 1) // APLL calibration trigger
- #define APLL_CALE (1 << 0) // APLL calibration enable
- #define BIM_CCNT 0xB4 // Calibration Counter Registers
- #define BIM_CCNTH 0xB4
- #define BIM_CCNTL 0xB5
- #endif
- #define BIM_FOFFH 0xB6 // Flash Offset Register
- #define BIM_FOFFL 0xB7
- #if (defined(MT1389_REV_HD) || defined(MT1389_REV_E) || defined(MT1389_REV_P) || defined(MT1389_REV_L) || defined(MT1389_REV_K))
- #define BIM_PLLS 0xB8
- #if (defined(MT1389_REV_L) || defined(MT1389_REV_K))
- #define PS_DMPLL_1 0x00
- #define PS_DMPLL_2 0x01
- // 0x03 reserved
- // 0x04 reserved
- #define PS_VPLL_1 0x04
- #define PS_VPLL_2 0x05
- #define PS_VPLL_3 0x06
- #define PS_VPLL_4 0x07
- #define PS_VPLL_5 0x08
- #define PS_VPLL_6 0x09
- #define PS_VPLL_7 0x0A
- #define PS_VPLL_8 0x0B
- #define DEN_VPLL (1<<7)
- #define PS_VPLL_9 0x0C
- #define PS_MISC_CTRL 0x18
- #define PS_DPL_DELAY 0x19
- #define PS_DPL_DUTY 0x1A
- #define PS_DRAM_CLK_1 0x1B
- #define PS_DRAM_CLK_2 0x1C
- #define PS_NEW_IO1_EN 0x1D
- #define PS_NEW_IO2_EN 0x1E
- #define PS_NEW_IO1_OUT 0x1F
- #define PS_NEW_IO2_OUT 0x20
- #define PS_NEW_IO1_IN 0x21
- #define PS_NEW_IO2_IN 0x22
- #define PS_8032_CLK 0x23
- #define PS_SM_CLK 0x24
- #define PS_MS_CLK 0x25
- #define PS_SD_CLK 0x26
- #define PS_SFI_CLK 0x29
- #define ACLK_PIN_SEL1 (1 << 0)
- #define ACLK_PIN_SEL2 (1 << 1)
- #define PS_FPD_VDOUT_CLK 0x2C
- #define PS_PIN_CTRL5 0x30
- #define SDATA0_PIN_SEL1 (1<<0)
- #define SDATA0_PIN_SEL2 (1<<1)
- #define MP_ADC_INTERFAACE_CONF0 0x31
- #define PS_ANALOG_PIN_CTRL1 0x31
- #define SPDIF_GPIO12_EN (1<<7)
- #define GPIO3_EN (1<<6)
- #define LR_GPIO10_EN (1<<5)
- #define UD_GPIO9_EN (1<<4)
- #define AKIN1_GPIO_EN (1<<3)
- #define ADVCM_GPIO_EN (1<<2)
- #define AKIN2_GPIO_EN (1<<1)
- #define FG_GPIO2_EN (1<<0)
- #define PS_ANALOG_PIN_CTRL2 0x32
- #define PS_MMU_CTRL_1 0x35 // New H/W common bank register
- #define PS_MMU_CTRL_2 0x36
- #define PS_MMU_CTRL_3 0x37
- #define PS_ROM_NC_ADDR 0x3C
- #define PS_ROM_C_ADDR 0x3D
- #define PS_ROM_DELAY_SEL 0x3E
- #define PS_ROM_CTRL 0x3F
- #elif defined (MT1389_REV_P)
- #define PS_DMPLL_1 0x00
- #define PS_DMPLL_2 0x01
- #define PS_DMPLL_3 0x02
- #define PS_DMPLL_4 0x03
- #define PS_DMPLL_5 0x04
- #define PS_DMPLL_6 0x05
- // 0x06 reserved
- // 0x07 reserved
- // 0x08 reserved
- // 0x09 reserved
- // 0x0A reserved
- // 0x0B reserved
- // 0x0C reserved
- // 0x0D reserved
- // 0x0E reserved
- #define PS_VPLL_1 0x0F
- #define PS_VPLL_2 0x10
- #define PS_VPLL_3 0x11
- #define PS_VPLL_4 0x12
- #define PS_VPLL_5 0x13
- #define PS_VPLL_6 0x14
- #define PS_VPLL_7 0x15
- #define PS_VPLL_8 0x16
- // 0x17 reserved
- #define PS_MISC_CTRL 0x18
- #define PS_DPL_DELAY 0x19
- #define PS_DPL_DUTY 0x1A
- #define PS_DRAM_CLK_1 0x1B
- #define PS_DRAM_CLK_2 0x1C
- #define PS_NEW_IO1_EN 0x1D
- #define PS_NEW_IO2_EN 0x1E
- #define PS_NEW_IO1_OUT 0x1F
- #define PS_NEW_IO2_OUT 0x20
- #define PS_NEW_IO1_IN 0x21
- #define PS_NEW_IO2_IN 0x22
- #define PS_8032_CLK 0x23
- //PS_FCI_CLK => SM/MS/SD
- #define PS_SM_CLK 0x24
- #define PS_MS_CLK 0x25
- #define PS_SD_CLK 0x26
- #define PS_TS_DEMUX_CLK 0x27
- #define PS_ATA_CLK 0x28
- #define PS_SFI_CLK 0x29
- #define PS_TVD_CLK 0x2A
- #define PS_VDOIN_CLK 0x2B
- #define PS_FPD_VDOUT_CLK 0x2C
- #define PS_SC_CLK 0x2D
- #define PS_SRV_RF_CTRL1 0x2E
- #define PS_SRV_RF_CTRL2 0x2F
- #define PS_PIN_CTRL5 0x30
- #define PS_ANALOG_PIN_CTRL1 0x31
- #define PS_ANALOG_PIN_CTRL2 0x32
- // 0x33 reserved
- #define PS_TS_DEMUX_CTRL 0x34
- //below is the definition that I dont know where to place it.
- //#define PS_PLL74_1 0x06
- //#define PS_PLL74_2 0x07
- //#define PS_PLL74_3 0x08
- //#define PS_PLL74_4 0x09
- //#define PS_PLL74_R 0x0A
- //#define PS_PLL74_K1 0x18
- //#define PS_pll74_K2 0x19
- #else
- #define PS_DMPLL_1 0x00
- #define PS_DMPLL_2 0x01
- #define PS_DMPLL_3 0x02
- #define PS_DMPLL_4 0x03
- #define PS_DMPLL_5 0x04
- #define PS_DMPLL_6 0x05
- #define PS_PLL74_1 0x06
- #define PS_PLL74_2 0x07
- #define PS_PLL74_3 0x08
- #define PS_PLL74_4 0x09
- #define PS_PLL74_R 0x0A
- #define PS_MISC_CTRL 0x0B
- #define PS_NEW_IO1_EN 0x0C
- #define PS_NEW_IO2_EN 0x0D
- #define PS_NEW_IO1_OUT 0x0E
- #define PS_NEW_IO2_OUT 0x0F
- #define PS_NEW_IO1_IN 0x10
- #define PS_NEW_IO2_IN 0x11
- #define PS_FCI_CLK 0x12
- #define PS_8032_CLK 0x13
- #define PS_DPL_DELAY 0x14
- #define PS_DPL_DUTY 0x15
- #define PS_DRAM_CLK_1 0x16
- #define PS_DRAM_CLK_2 0x17
- #define PS_PLL74_K1 0x18
- #define PS_pll74_K2 0x19
- #endif
- #define BIM_PLLD 0xB9
- #define PD_1_PD (0x01 << 7)
- #define PD_1_RST (0x01 << 6)
- #define PD_1_TET_1 (0x01 << 6)
- #define PD_4_DIV_1 0x00
- #define PD_4_DIV_2 0x01
- #define PD_5_K_TRIG (0x01 << 7)
- #define PD_5_DMPLL (0x00 << 5)
- #define PD_5_DMPLL_2 (0x01 << 5)
- #define PD_5_DMPLL_4 (0x10 << 5)
- #define PD_5_DMPLL_8 (0x11 << 5)
- #define PD_5_K_RDY (0x01 << 4)
- #else // MT1389_REV_HD || MT1389_REV_E
- #define BIM_DMPLLC 0xB8 // DMPLL Control Register
- #define DMPLL_PD (1 << 0) // DMPLL Power Down
- #define DMPLL_BD (1 << 1) // DMPLL band select
- #define DMPLL_TST (1 << 2) // DMPLL test mode
- #define BIM_DMPLLO 0xB9 // DMPLL Coefficient Register
- #endif // MT1389_REV_HD || MT1389_REV_E
- #ifdef MT1389_REV_E
- // BIM_PLLS
- #undef PS_PLL74_1
- #undef PS_PLL74_2
- #undef PS_PLL74_3
- #undef PS_PLL74_4
- #undef PS_PLL74_R
- #undef PS_NEW_IO2_EN
- #undef PS_NEW_IO2_OUT
- #undef PS_NEW_IO2_IN
- #undef PS_FCI_CLK
- #undef PS_PLL74_K1
- #undef PS_pll74_K2
- #define PS_CMN_CODE_CTRL 0x20
- #define PS_CMN_CODE_SZ 0x21
- #define PS_BANK1_ADDR_HI 0x22
- #define PS_BANK1_ADDR_LO 0x23
- #define PS_BANK2_ADDR_HI 0x24
- #define PS_BANK2_ADDR_LO 0x25
- #define PS_BANK3_ADDR_HI 0x26
- #define PS_BANK3_ADDR_LO 0x27
- #define PS_BANK4_ADDR_HI 0x28
- #define PS_BANK4_ADDR_LO 0x29
- #define PS_BANK5_ADDR_HI 0x2A
- #define PS_BANK5_ADDR_LO 0x2B
- #define PS_BANK6_ADDR_HI 0x2C
- #define PS_BANK6_ADDR_LO 0x2D
- #define PS_BANK7_ADDR_HI 0x2E
- #define PS_BANK7_ADDR_LO 0x2F
- #define PS_TRAP0_ADDR_EN 0x30
- #define PS_TRAP1_ADDR_EN 0x31
- #define PS_TRAP2_ADDR_EN 0x32
- #define PS_TRAP3_ADDR_EN 0x33
- #define PS_TRAP4_ADDR_EN 0x34
- #define PS_TRAP5_ADDR_EN 0x35
- #define PS_TRAP6_ADDR_EN 0x36
- #define PS_TRAP7_ADDR_EN 0x37
- #define PS_TRAP8_ADDR_EN 0x38
- #define PS_TRAP9_ADDR_EN 0x39
- #define PS_TRAPA_ADDR_EN 0x3A
- #define PS_TRAPB_ADDR_EN 0x3B
- #define PS_TRAPC_ADDR_EN 0x3C
- #define PS_TRAPD_ADDR_EN 0x3D
- #define PS_TRAPE_ADDR_EN 0x3E
- #define PS_TRAPF_ADDR_EN 0x3F
- #define PS_ROM_NC_ADDR 0xF0
- #define PS_ROM_C_ADDR 0xF1
- #define PS_ROM_DELAY_SEL 0xF2
- #define PS_ROM_CTRL 0xF3
- // BIM_PLLD
- #endif // MT1389_REV_E
- #ifdef MT1389_REV_L // AceBest_Lin 89LRomCode
- #define PS_CMN_CODE_CTRL 0x20
- #define PS_CMN_CODE_SZ 0x21
- #define PS_BANK1_ADDR_HI 0x22
- #define PS_BANK1_ADDR_LO 0x23
- #define PS_BANK2_ADDR_HI 0x24
- #define PS_BANK2_ADDR_LO 0x25
- #define PS_BANK3_ADDR_HI 0x26
- #define PS_BANK3_ADDR_LO 0x27
- #define PS_BANK4_ADDR_HI 0x28
- #define PS_BANK4_ADDR_LO 0x29
- #define PS_BANK5_ADDR_HI 0x2A
- #define PS_BANK5_ADDR_LO 0x2B
- #define PS_BANK6_ADDR_HI 0x2C
- #define PS_BANK6_ADDR_LO 0x2D
- #define PS_BANK7_ADDR_HI 0x2E
- #define PS_BANK7_ADDR_LO 0x2F
- #define PS_TRAP0_ADDR_EN 0x40
- #define PS_TRAP1_ADDR_EN 0x41
- #define PS_TRAP2_ADDR_EN 0x42
- #define PS_TRAP3_ADDR_EN 0x43
- #define PS_TRAP4_ADDR_EN 0x44
- #define PS_TRAP5_ADDR_EN 0x45
- #define PS_TRAP6_ADDR_EN 0x46
- #define PS_TRAP7_ADDR_EN 0x47
- #define PS_TRAP0_ADDR_LO 0x48 // 8 : 1
- #define PS_TRAP0_ADDR_MI 0x49 // 16 : 9
- #define PS_TRAP0_ADDR_HI 0x4A // 24 :17
- #define PS_TRAP1_ADDR_LO 0x50
- #define PS_TRAP1_ADDR_MI 0x51
- #define PS_TRAP1_ADDR_HI 0x52
- #define PS_TRAP2_ADDR_LO 0x53
- #define PS_TRAP2_ADDR_MI 0x54
- #define PS_TRAP2_ADDR_HI 0x55
- #define PS_TRAP3_ADDR_LO 0x56
- #define PS_TRAP3_ADDR_MI 0x57
- #define PS_TRAP3_ADDR_HI 0x58
- #define PS_PATCH0_ADDR_LO 0x60
- #define PS_PATCH0_ADDR_MID 0x61
- #define PS_PATCH0_ADDR_HI 0x62
- #define PS_PATCH1_ADDR_LO 0x63
- #define PS_PATCH1_ADDR_MID 0x64
- #define PS_PATCH1_ADDR_HI 0x65
- #define PS_PATCH2_ADDR_LO 0x66
- #define PS_PATCH2_ADDR_MID 0x67
- #define PS_PATCH2_ADDR_HI 0x68
- #define PS_PATCH3_ADDR_LO 0x69
- #define PS_PATCH3_ADDR_MID 0x6a
- #define PS_PATCH3_ADDR_HI 0x6b
- #endif // MT1389_REV_L
- #if defined(MT1389_REV_P) || defined(MT1389_REV_L) || defined(MT1389_REV_K)
- #define BIM_AN_H 0xBA // APLL Divide-N[8:15] Register
- #define BIM_AML 0xBB // APLL Divide-M Register
- #define BIM_AMH 0xBC
- #define BIM_AK 0xBD //APLL Divider AK
- #define BIM_APLL_CAL_CNTH 0xBE ////APLL calibration[8:11]
- #else
- #define BIM_AMH 0xBA // APLL Divide-M Register
- #define BIM_AML 0xBB
- #define BIM_AN1 0xBC // APLL Divide-N1 Register
- #define AN1_D8 0x00 // Divide 8
- #define AN1_D9 0x01 // Divide 9
- #define AN1_D10 0x02 // Divide 10
- #define AN1_D11 0x03 // Divide 11
- #define AN1_D12 0x04 // Divide 12
- #define BIM_AN2H 0xBD // APLL Divide-N2 Register
- #define BIM_AN2L 0xBE
- #endif
- #if defined(MT1389_REV_E) || defined(MT1389_REV_HD) || defined(MT1389_REV_P)|| defined(MT1389_REV_L) || defined(MT1389_REV_K)
- #define CLK_NO_APPLY 0x0 // Which means won't work if you set here. by Alfonso.
- #define BIM_RCLKC 0xBF // RISC Clock Control Register
- #if defined(MT1389_REV_L) || defined(MT1389_REV_K)
- #define RC_27M 0x00 // 27MHz
- #define RC_DPLD2_0D 0x01 // DMPLL clock divided by 2 with 0 degree phrase
- #define RC_DLL_108M 0x02 // DLL 108M
- #define RC_DPLD2 0x05 // DMPLL clock divided by 2
- #define RC_DPLD3 0x06 // DMPLL clock divided by 3
- #define RC_DPLD4 0x07 // DMPLL clock divided by 4
- #define RC_CLK_MASK 0x07
- #define RCLK_PD (1 << 7) // RISC Clock Power Down
- #else
- #define RC_27M 0x00 // 27MHz
- #define RC_APLD2 0x01 // APLL clock divided by 2
- #define RC_DPLD2_0D 0x02 // DMPLL clock divided by 2 with 0 degree phrase
- #ifdef MT1389_REV_P
- #define RC_162M 0x03 // 324M divided by 2
- #define RC_130M 0x04 // 324M divided by 2.5
- #else /*! MT1389_REV_P*/
- #define RC_DPLD2_90D 0x03 // DMPLL clock divided by 2 with 90 degree phrase
- #define RC_DPLD2_270D 0x04 // DMPLL clock divided by 2 with 270 degree phrase
- #endif
- #define RC_DPLD2 0x05 // DMPLL clock divided by 2
- #define RC_DPLD3 0x06 // DMPLL clock divided by 3
- #define RC_DPLD4 0x07 // DMPLL clock divided by 4
- #define RC_CLK_MASK 0x07
- #define RCLK_PD (1 << 7) // RISC Clock Power Down
- #endif
- #define BIM_ACLKC 0xC0 // Audio DSP Clock Control Register
- #if defined(MT1389_REV_L) || defined(MT1389_REV_K)
- #define AC_27M 0x00 // 27MHz
- #define AC_APLD2 0x01 // APLL clock divided by 2
- #define AC_DPLD2_0D 0x02 // DMPLL clock divided by 2 with 0 degree phrase
- #define AC_DPLD2 0x05 // DMPLL clock divided by 2
- #define AC_DPLD3 0x06 // DMPLL clock divided by 3
- #define AC_DPLD4 0x07 // DMPLL clock divided by 4
- #define AC_CLK_MASK 0x07
- #define ACLK_PD (1 << 7) // Audio DSP Clock Power Down
- #else
- #define AC_27M 0x00 // 27MHz
- #define AC_APLD2 0x01 // APLL clock divided by 2
- #define AC_DPLD2_0D 0x02 // DMPLL clock divided by 2 with 0 degree phrase
- #ifdef MT1389_REV_P
- #define RC_162M 0x03 // 324M divided by 2
- #define RC_130M 0x04 // 324M divided by 2.5
- #else /*! MT1389_REV_P*/
- #define AC_DPLD2_90D 0x03 // DMPLL clock divided by 2 with 90 degree phrase
- #define AC_DPLD2_270D 0x04 // DMPLL clock divided by 2 with 270 degree phrase
- #endif
- #define AC_DPLD2 0x05 // DMPLL clock divided by 2
- #define AC_DPLD3 0x06 // DMPLL clock divided by 3
- #define AC_DPLD4 0x07 // DMPLL clock divided by 4
- #define AC_CLK_MASK 0x07
- #define ACLK_PD (1 << 7) // Audio DSP Clock Power Down
- #endif
- #define BIM_PCLKC 0xC1 // uP Clock Control Register
- #if defined(MT1389_REV_L) || defined(MT1389_REV_K)
- #define PC_7M 0x00 // 27M/4 clock
- #define PC_13M 0x01 // 27M/2 clock
- #define PC_27M 0x02 // 27M clock
- #define PC_DLL_108M2 0x03 // DLL 108M/2
- #define PC_DPLD8 0x04 // DMPLL /8
- #define PC_DPL_CNTR 0x05 // DMPLL divided by the value of 8032 Counter (0xF8B8=0x23)
- #define PC_SDCD5 0x06 // Source decode clock divided 5
- #define PC_SDCD6 0x07 // Source decode clock divided 6
- #else
- #define PC_7M 0x00 // 27M/4 clock
- #define PC_13M 0x01 // 27M/2 clock
- #define PC_27M 0x02 // 27M clock
- #define PC_LOCAL_OSC 0x03
- #define PC_DPLD16 0x04
- #define PC_DPL_CNTR 0x05 // MT1389HD
- #define PC_SDCD5 0x06
- #define PC_SDCD6 0x07
- #endif
- // The value apply on 0xF8C2[2:0] won't work for DRAM setting.
- #define BIM_DCLKC 0xC2 // DRAM Clock Control Register
- #define DC_27M 0x00 // 27MHz
- #define DC_DLL_108M 0x01 // DLL 108M
- #define DC_DPLD2_0D 0x02 // DMPLL clock divided by 2 with 0 degree phrase
- #define DC_DPLD2_90D 0x03 // DMPLL clock divided by 2 with 90 degree phrase
- #define DC_DPLD2_270D 0x04 // DMPLL clock divided by 2 with 270 degree phrase
- #define DC_DPLD2 0x05 // DMPLL clock divided by 2
- #define DC_DPLD3 0x06 // DMPLL clock divided by 3
- #define DC_DPLD4 0x07 // DMPLL clock divided by 4
- #define DC_CLK_MASK 0x07
- #define DCLK_SB (1 << 6) // DRAM clock standby
- #define DCLK_PD (1 << 7) // DRAM clock Power Down
- #if defined(MT1389_REV_L) || defined(MT1389_REV_K)
- #else
- #define DC_27M 0x00 // 27MHz
- #define DC_APLD2 0x01 // APLL clock divided by 2
- #define DC_DPLD2_0D 0x02 // DMPLL clock divided by 2 with 0 degree phrase
- #define DC_DPLD2_90D 0x03 // DMPLL clock divided by 2 with 90 degree phrase
- #define DC_DPLD2_270D 0x04 // DMPLL clock divided by 2 with 270 degree phrase
- #define DC_DPLD2 0x05 // DMPLL clock divided by 2
- #define DC_DPLD3 0x06 // DMPLL clock divided by 3
- #define DC_DPLD4 0x07 // DMPLL clock divided by 4
- #define DC_CLK_MASK 0x07
- #define DCLK_SB (1 << 6) // DRAM clock standby
- #define DCLK_PD (1 << 7) // DRAM clock Power Down
- #endif
- #define BIM_SDCLKC 0xC3 // Source Decode Clock Control Register
- #if defined(MT1389_REV_L) || defined(MT1389_REV_K)
- #define SDC_27M 0x00 // 27MHz
- #define SDC_DLL_108M 0x04 // DLL 108M
- #define SDC_DPLD2 0x05 // DMPLL clock divided by 2
- #define SDC_DPLD3 0x06 // DMPLL clock divided by 3
- #define SDC_DPLD4 0x07 // DMPLL clock divided by 4
- #define SDC_CLK_MASK 0x07
- #define SDCLK_PD (1 << 7) // Source Decode Clock Power Down
- #else
- #define SDC_27M 0x00 // 27MHz
- #ifdef MT1389_REV_P
- #define SDC_APLD2 0x01 // APLL clock divided by 2
- #define SDC_162M 0x02 // 324M divided by 2
- #define SDC_108M 0x03 // 324M divided by 3
- #define SDC_81M 0x04 // 324M divided by 4
- #endif /* MT1389_REV_P */
- #define SDC_DPLD2 0x05 // DMPLL clock divided by 2
- #define SDC_DPLD3 0x06 // DMPLL clock divided by 3
- #define SDC_DPLD4 0x07 // DMPLL clock divided by 4
- #define SDC_CLK_MASK 0x07
- #define SDCLK_PD (1 << 7) // Source Decode Clock Power Down
- #endif
- #define BIM_CDCLKC 0xC4 // Channel Decode Clock Control Register
- #define CDC_SDCD2 0x00 // Source decode clock divided by 2
- #define CDC_SDCD4 0x01 // Source decode clock divided by 4
- #define CDC_27M 0x02 // 27M
- #define CDC_27MD2 0x03 // 27M clock divided by 2
- #define CDC_27MD4 0x04 // 27M clock divided by 4
- #define CDC_CLK_MASK 0x07
- #define CDCLK_PD (1 << 7) // Channel Decode Clock Power Down
- #define BIM_SCLKC 0xC5 // Servo DSP Clock Control Register
- #define SC_27M 0x00 // 27M clock
- #if 0
- #define SC_APLD2 0x01 // APLL clock divided by 2
- #define SC_APLD3 0x02 // APLL clock divided by 3
- #define SC_APLD4 0x03 // APLL clock divided by 4
- #define SC_APLD5 0x04 // APLL clock divided by 5
- #endif /* if 0 */
- #define SC_DPLD2 0x05 // DMPLL clock divided by 2
- #define SC_DPLD3 0x06 // DMPLL clock divided by 3
- #define SC_DPLD4 0x07 // DMPLL clock divided by 4
- #define SCLK_PD (1 << 7) // Servo DSP Clock Power Down
- #else /*!defined(MT1389_REV_E) && !defined(MT1389_REV_HD)*/
- #define BIM_RCLKC 0xBF // RISC Clock Control Register
- #define RC_27M 0x00 // 27MHz
- #define RC_APLD2 0x01 // APLL clock divided by 2
- #define RC_DPL2D2 0x02 // APLL clock divided by 3
- #define RC_DPL2D3 0x03 // APLL clock divided by 4
- #define RC_DPL2D4 0x04 // APLL clock divided by 5
- #define RC_DPLD2 0x05 // DMPLL clock divided by 2
- #define RC_DPLD3 0x06 // DMPLL clock divided by 3
- #define RC_DPLD4 0x07 // DMPLL clock divided by 4
- #define RC_CLK_MASK 0x07
- #define RCLK_PD (1 << 7) // RISC Clock Power Down
- #define BIM_ACLKC 0xC0 // Audio DSP Clock Control Register
- #define AC_27M 0x00 // 27MHz
- #define AC_APLD2 0x01 // APLL clock divided by 2
- #define AC_DPL2D2 0x02 // APLL clock divided by 3
- #define AC_DPL2D3 0x03 // APLL clock divided by 4
- #define AC_DPL2D4 0x04 // APLL clock divided by 5
- #define AC_DPLD2 0x05 // DMPLL clock divided by 2
- #define AC_DPLD3 0x06 // DMPLL clock divided by 3
- #define AC_DPLD4 0x07 // DMPLL clock divided by 4
- #define AC_CLK_MASK 0x07
- #define ACLK_PD (1 << 7) // Audio DSP Clock Power Down
- #define BIM_PCLKC 0xC1 // uP Clock Control Register
- #define PC_7M 0x00 // 27M/4 clock
- #define PC_13M 0x01 // 27M/2 clock
- #define PC_27M 0x02 // 27M clock
- #define PC_LOCAL_OSC 0x03
- #define PC_DPLD16 0x04
- #define PC_DPL2D16 0x05
- #define PC_DPL_CNTR 0x05 // MT1389HD
- #define PC_SDCD5 0x06
- #define PC_SDCD6 0x07
- #define BIM_DCLKC 0xC2 // DRAM Clock Control Register
- #define DC_27M 0x00 // 27MHz
- #define DC_APLD2 0x01 // APLL clock divided by 2
- #define DC_DPL2D2 0x02 // APLL clock divided by 3
- #define DC_DPL2D3 0x03 // APLL clock divided by 4
- #define DC_DPL2D4 0x04 // APLL clock divided by 5
- #define DC_DPLD2 0x05 // DMPLL clock divided by 2
- #define DC_DPLD3 0x06 // DMPLL clock divided by 3
- #define DC_DPLD4 0x07 // DMPLL clock divided by 4
- #define DC_CLK_MASK 0x07
- #define DCLK_SB (1 << 6) // DRAM clock standby
- #define DCLK_PD (1 << 7) // DRAM clock Power Down
- #define BIM_SDCLKC 0xC3 // Source Decode Clock Control Register
- #define SDC_27M 0x00 // 27MHz
- #define SDC_DPL2D2 0x01 // APLL clock divided by 3
- #define SDC_DPL2D3 0x02 // APLL clock divided by 4
- #define SDC_DPL2D4 0x03 // APLL clock divided by 5
- #define SDC_DPL2D5 0x04 // APLL clock divided by 6
- #define SDC_DPLD2 0x05 // DMPLL clock divided by 2
- #define SDC_DPLD3 0x06 // DMPLL clock divided by 3
- #define SDC_DPLD4 0x07 // DMPLL clock divided by 4
- #define SDC_CLK_MASK 0x07
- #define SDCLK_PD (1 << 7) // Source Decode Clock Power Down
- #define BIM_CDCLKC 0xC4 // Channel Decode Clock Control Register
- #define CDC_SDCD2 0x00 // Source decode clock divided by 2
- #define CDC_SDCD4 0x01 // Source decode clock divided by 4
- #define CDC_27M 0x02 // 27M
- #define CDC_27MD2 0x03 // 27M clock divided by 2
- #define CDC_27MD4 0x04 // 27M clock divided by 4
- #define CDC_CLK_MASK 0x07
- #define CDCLK_PD (1 << 7) // Channel Decode Clock Power Down
- #define BIM_SCLKC 0xC5 // Servo DSP Clock Control Register
- #define SC_27M 0x00 // 27M clock
- #define SC_APLD2 0x01 // APLL clock divided by 2
- #define SC_APLD3 0x02 // APLL clock divided by 3
- #define SC_APLD4 0x03 // APLL clock divided by 4
- #define SC_APLD5 0x04 // APLL clock divided by 5
- #define SC_DPLD2 0x05 // DMPLL clock divided by 2
- #define SC_DPLD3 0x06 // DMPLL clock divided by 3
- #define SC_DPLD4 0x07 // DMPLL clock divided by 4
- #define SCLK_PD (1 << 7) // Servo DSP Clock Power Down
- #endif /* defined(MT1389_REV_E) || defined(MT1389_REV_HD) */
- #define BIM_AOCLKC 0xC6 // Audio out Clock Control Register
- #define AOC_APL27M 0x00
- #define AOC_APLN1 0x01 // APLL-N1 clock
- #define AOC_APLN1D2 0x02 // APLL-N1 clock divided by 2
- #define AOC_APLN1D3 0x03 // APLL-N1 clock divided by 3
- #define AOC_APLN1D4 0x04 // APLL-N1 clock divided by 4
- #define AOC_APLN1D6 0x05 // APLL-N1 clock divided by 6
- #define AOC_APLD4 0x06 // APLL clock divided by 4
- #define AOC_APLD5 0x07 // APLL clock divided by 5
- #define AOC_NORMAL 0x00 // Normal mode
- #define AOC_1D2 0x08 // divided by 2 mode
- #define AOC_1D4 0x10 // divided by 4 mode
- #define AOC_1D3 0x18 // divided by 3 mode
- #define AOC_2D3_66 0x20 // divided by 2/3 mode (duty cycle 66%)
- #define AOC_2D3_33 0x21 // divided by 2/3 mode (duty cycle 33%)
- #define AOCLK_PD (1 << 7) // Audio out Clock Power Down
- /*
- #define BIM_PL33C 0xC7 // PL33 Clock Control Register
- #define P3C_27M 0x00 // 27MHz
- #define P3C_APLD11 0x06 // APLL clock divided by 11
- #define P3C_APLD10 0x05 // APLL clock divided by 10
- #define P3C_APLD9 0x04 // APLL clock divided by 9
- #define P3C_APLD8 0x03 // APLL clock divided by 8
- #define P3C_APLD7 0x02 // APLL clock divided by 7
- #define P3C_APLN1 0x01 // APLL N1 clock
- #define PL33_PD (1 << 7) // PL33 Clock Power Down
- */
- #define BIM_DMPLL2 0xC7 // DMPLL2 Coefficient Register, non valid in 89E/HD
- #define BIM_XCKC 0xC8 // XCK Clock Control Register
- #define X4S_27M 0x80 // RF interface clock 27M
- #define X4S_PL33 0x40 // RF interface clock PLL33
- #define XCKC_SETTING (X4S_27M)
- #define BIM_FOFFS 0xC9 // Flash offset select register
- #define BIM_DSTS 0xCA // Channel Decode Status Register
- #define CDRB (1 << 3) // 1:CD data buffering BUSY
- #define CDDB (1 << 2) // 1:CD decoding BUSY
- #define DVDRB (1 << 1) // 1:DVD data buffering BUSY
- #define DVDDB (1 << 0) // 1:DVD decoding BUSY
- #define BIM_OPD1H 0xCB // Operand 1 High Register
- #define BIM_OPD1M 0xCC // Operand 1 Middle Register
- #define BIM_OPD1L 0xCD // Operand 1 Low Register
- #define BIM_OPD2H 0xCE // Operand 2 High Register
- #define BIM_OPD2M 0xCF // Operand 2 Middle Register
- #define BIM_OPD2L 0xD0 // Operand 2 Low Register
- #define BIM_OPR 0xD1 // Operation Register
- #define OPR_MUL 0x01 // 1: Multiplication
- #define OPR_DIV 0x02 // 1: Division
- #define OPR_ADD 0x03 // Addition
- #define OPR_SUB 0x04 // Subtraction
- #define OPR_SQRT 0x05 // Square Root Extraction
- #define OPR_NEG 0x06 // Negation
- #define OPR_ZONE 0x07 // Zoning
- #define OPR_CST_1 0x10 // Constant 1
- #define OPR_CST_7 0x20 // Constant 7
- #define OPR_CST_16 0x30 // Constant 16
- #define OPR_CST_60 0x40 // Constant 60
- #define OPR_CST_75 0x50 // Constant 75
- #define OPR_CST_100 0x60 // Constant 100
- #define OPR_CST_150 0x70 // Constant 150
- #define OPR_CST_TRKPZ 0x80 // Constant Tracks/Zone
- #define OPR_CST_30000 0x90 // Constant 0x30000
- #define OPR_CST_31000 0xA0 // Constant 0x31000
- #define BIM_CERR 0xD2
- #define BIM_TEST 0xD3
- #define BIM_CKOUT 0xD4
- #define BIM_RDMA 0xD5 // ROM DMA control register
- #define WOOF (1 << 1) // without flash offset address
- #define RDMA_ST (1 << 0) // DMA trigger/status
- //#define BIM_EARRH 0xD6
- //#define BIM_EARRM 0xD7
- //#define BIM_EARRL 0xD8
- #define BIM_CHSUMH 0xD6
- #define BIM_CHSUML 0xD7
- #define BIM_DM2C 0xD8
- #define BIM_PCTL3 0xD9 // Pin control register 3
- #define MCOFF (1 << 7) // Microphone in is used as I/O pin
- #define SOFF4 (1 << 6) // Sdata4 is used as I/O pin
- #define SOFF3 (1 << 5) // Sdata3 is used as I/O pin
- #define SOFF2 (1 << 4) // Sdata2 is used as I/O pin
- #define SOFF1 (1 << 3) // Sdata1 is used as I/O pin
- #define SOFF0 (1 << 2) // Sdata0 is output with 0
- #define AUCLKOFF (1 << 1) // Audio clock pins' GPIO control
- #define BIM_IRTHD 0xDA // IR threshold register
- #define BIM_PCTL4 0xDB // Pin control register 4
- #define LINE_IN_SPDATA 0x00 // Audio line-in from SPDATA
- #define LINE_IN_IOA20 0x01 // Audio line-in from IOA20
- #define LINE_IN_YUV7 0x02 // Audio line-in from YUV7
- #define LINE_IN_HSYN 0x03 // Audio line-in from HSYN
- #define LINE_IN_VSYN 0x04 // Audio line-in from VSYN
- #define LINE_IN_BLANK 0x05 // Audio line-in from BLANK
- #define LINE_IN_ASDATA4 0x06 // Audio line-in from ASDATA4
- #define LINE_IN_ASDATA3 0x07 // Audio line-in from ASDATA3
- #define BIM_VCK4M 0xDC
- #define BIM_BIST 0xDD
- #define BIM_BISTS 0xDE
- #define BIM_BISTEN 0xDF
- #define BIM_GPR0 0xE0 // General Purpose Registers 0
- #define BIM_GPR1 0xE1 // General Purpose Registers 1
- #define BIM_GPR2 0xE2 // General Purpose Registers 2
- #define BIM_GPR3 0xE3 // General Purpose Registers 3
- #define BIM_GPR4 0xE4 // General Purpose Registers 4
- #define BIM_GPR5 0xE5 // General Purpose Registers 5
- #define BIM_GPR6 0xE6 // General Purpose Registers 6
- #define BIM_GPR7 0xE7 // General Purpose Registers 7
- #define BIM_GPR8 0xE8 // General Purpose Registers 8
- #define BIM_GPR9 0xE9 // General Purpose Registers 9
- #define BIM_GPRA 0xEA // General Purpose Registers A
- #define BIM_GPRB 0xEB // General Purpose Registers B
- #define BIM_GPRC 0xEC // General Purpose Registers C
- #define BIM_GPRD 0xED // General Purpose Registers D
- #define BIM_GPRE 0xEE // General Purpose Registers E
- #define BIM_GPRF 0xEF // General Purpose Registers F
- #define BIM_RIODRH 0xF0 // RAM GPIO direction registers
- #define BIM_RIODRM 0xF1 // RAM GPIO direction registers
- #define BIM_RIODRL 0xF2 // RAM GPIO direction registers
- #define BIM_RIODOH 0xF3 // RAM GPIO data out registers
- #define BIM_RIODOM 0xF4 // RAM GPIO data out registers
- #define BIM_RIODOL 0xF5 // RAM GPIO data out registers
- #define BIM_RIODIH 0xF6 // RAM GPIO data in registers
- #define BIM_RIODIM 0xF7 // RAM GPIO data in registers
- #define BIM_RIODIL 0xF8 // RAM GPIO data in registers
- #define IOH_UP12 (1 << 7) //up12
- #define IOH_MC (1 << 6)
- #define IOH_SDATA4 (1 << 5)
- #define IOH_SDATA3 (1 << 4)
- #define IOH_SDATA2 (1 << 3)
- #define IOH_SDATA1 (1 << 2)
- #define IOH_DQM3 (1 << 1)
- #define IOH_DQM2 (1 << 0)
- #define IOM_RD31 (1 << 7)
- #define IOM_RD30 (1 << 6)
- #define IOM_RD29 (1 << 5)
- #define IOM_RD28 (1 << 4)
- #define IOM_RD27 (1 << 3)
- #define IOM_RD26 (1 << 2)
- #define IOM_RD25 (1 << 1)
- #define IOM_RD24 (1 << 0)
- #define IOL_RD23 (1 << 7)
- #define IOL_RD22 (1 << 6)
- #define IOL_RD21 (1 << 5)
- #define IOL_RD20 (1 << 4)
- #define IOL_RD19 (1 << 3)
- #define IOL_RD18 (1 << 2)
- #define IOL_RD17 (1 << 1)
- #define IOL_RD16 (1 << 0)
- // MT1389_REV_D only
- #define IOL_FG (1 << 6)
- #define IOL_AR (1 << 5)
- #define IOL_AL (1 << 4)
- #define IOL_ASDATA0 (1 << 3)
- #define IOL_ALRCK (1 << 2)
- #define IOL_ABCK (1 << 1)
- #define IOL_ACLK (1 << 0)
- #define IOL_BCK (1 << 1)
- #define IOL_CLK (1 << 0)
- #define BIM_SFIS 0xFD
- #define BIM_SFID 0xFE
- //////////////////////////////////////////////////////
- // Audio registers definition
- #define AUD_RSDATA 0x00 // RS-232 data register
- #define AUD_RSSTA 0x01 // RS-232 status register
- #define WALLOW (1 << 1) // Write data buiffer empty
- #define RALLOW (1 << 0) // Read data available
- #if defined(MT1389_REV_P) || defined(MT1389_REV_L) || defined(MT1389_REV_K)
- #define AUD_ADACDITH0 0x20 //for 89P
- #define NO_MUTE_PIN (0<<5)
- #define GPIO10_MUTE (1<<5)
- #define IOALE_MUTE (2<<5)
- #define RD_MUTE (3<<5)
- #if defined(MT1389_REV_L ) || defined(MT1389_REV_K)
- #define AKIN2_MUTE (1<<6)
- #define AKIN1_MUTE (1<<5)
- #endif
- //#else
- #define AUD_ADSPSEL 0x20 // DSP Selected for Servo Control
- #define M2DRS (1 << 1)
- #define ADSP_SEL (1 << 0)
- #else
- #define AUD_ADSPSEL 0x20 // DSP Selected for Servo Control
- #define M2DRS (1 << 1)
- #define ADSP_SEL (1 << 0)
- #endif
- #define AUD_AOUTCFG 0x22 // Audio Output Configuration
- #define INV_LRCK (1 << 7) // Invert LRCK
- #define INV_BCK (1 << 6) // Invert bit clock
- #define AOFMT_RJ (0 << 4) // Right aligned with LRCK
- #define AOFMT_LJ (2 << 4) // Left aligned with LRCK
- #define AOFMT_I2S (3 << 4) // I2S interface
- #define LRCK_CYC16 (0 << 0) // 16 cycles
- #define LRCK_CYC24 (1 << 0) // 24 cycles
- #define LRCK_CYC32 (2 << 0) // 32 cycles
- #define DSD_MASK (1 << 3) // bit3 for DSD output
- #define AUD_ADACCFG 0x23 // Audio DAC Configuration
- #define INV_SD (1 << 6) // Invert the Sdata output
- #define DAC_BNUM_MASK 0x3F // Audio DAC bit number
- #define DAC_16BIT 0x10 // Audio DAC 16-Bit
- #define DAC_18BIT 0x12 // Audio DAC 18-Bit
- #define DAC_20BIT 0x14 // Audio DAC 20-Bit
- #define DAC_24BIT 0x18 // Audio DAC 24-Bit
- #define AUD_ACLKCFG 0x24 // Audio Clock Configuration
- #define ACK_128FS (1 << 5) // ACK is 128 times of audio frequency
- #define ACK_256FS (2 << 5) // ACK is 256 times of audio frequency
- #define ACK_384FS (3 << 5) // ACK is 384 times of audio frequency
- #define ACK_512FS (4 << 5) // ACK is 384 times of audio frequency
- #define ACK_EXSEL (1 << 4) // External ACK select
- #define A2BCKX_MASK 0x0F // Times of ACK/2 to BCK
- #define AUD_IECCFG 0x25 // IEC958 Configuration
- #define IEC_CUR_4 (1 << 5) // IEC958 driving current 4mA
- #define IEC_SSLEW (1 << 4) // IEC958 output slow slew rate
- #define IEC_CH78 (1 << 2) // Use this pin as channel 7/8
- #define IEC_B21 (1 << 1) // IEC channel status bit 21
- #define IEC_B20 (1 << 0) // IEC channel status bit 20
- #define AUD_BSCFG 0x26 // Bit Stream Configuration
- #define IEC_SWP (1 << 1) // Swap IEC raw data output high & low bytes
- #define BS_SWP (1 << 0) // Swap bitstream high & low bytes
- #define AUD_MPINCFG 0x28 // Micro Phone ADC Interface Configuration
- #define MP_DATDLY (1 << 6) // Microphone serial data start cycle delay
- #define MP_LALN (1 << 5) // Microphone serial data is left aligned to LRCK
- #define MP_BNUM_MASK 0x1F // (numbers of bits - 1) for microphone ADC
- #define MP_16BIT 0x0F // 16 bits
- #define MP_18BIT 0x11 // 18 bits
- #define MP_20BIT 0x13 // 20 bits
- #define MP_24BIT 0x17 // 24 bits
- #define AUD_MPINCFG1 0x31 // Micro Phone ADC Interface Configuration 1
- #define SDATA5_SEL_OFF 0x00
- #define SDATA5_SEL_YUV7 0x10
- #define SDATA5_SEL_SPBCK 0x20
- #define SDATA5_SEL_RD31 0x30
- #define AUD_SPLIN0 0x34 // SPDIF/line in configuration interface 0
- #define SPLIN_INV (1 << 7) // SPDIF/line in LRCK is inverted
- #define SPLIN_RJ (0 << 5) // Right aligned with LRCK
- #define SPLIN_LJ (1 << 5) // Left aligned with LRCK
- #define SPLIN_I2S (3 << 5) // I2S interface
- #define SPLIN_BNUM_MASK 0x1F // (number of bits - 1) for line in ADC or SPDIF
- #define SPLIN_16BIT 0x0F // 16 bits
- #define SPLIN_18BIT 0x11 // 18 bits
- #define SPLIN_20BIT 0x13 // 20 bits
- #define SPLIN_24BIT 0x17 // 24 bits
- #define AUD_SPLIN1 0x35 // SPDIF/line in configuration interface 1
- #define SPDIF_IN (1 << 4) // The interface is line in
- #define SPDIF_CYC16 (0 << 0) // 16 cycles
- #define SPDIF_CYC24 (1 << 0) // 24 cycles
- #define SPDIF_CYC32 (2 << 0) // 32 cycles
- #if (defined(MT1389_REV_P) || defined(MT1389_REV_L) || defined(MT1389_REV_K))
- #define ADAC_CTRL0 0x02
- #define ADAC_OSR (0x03<<6)
- #define ADAC_INV_MOD_OUT (1<<5)
- #define ADAC_INV_SCF_CLK (1<<4)
- #define ADAC_INV_MOD_CLK (1<<3)
- #define ADAC_INV_LPF_CLK (1<<2)
- #define ADAC_INV_LRCK (1<<1)
- #define ADAC_MUTE (1<<0)
- #define ADAC_CTRL01 0x03
- #define ADAC_MOD_SEL (1<<4)
- #define ADAC_MOD_OUT_DELAY (0x0B)
- #define ADAC_DITH1 0x04
- #define ADAC_COEFF_A3 (0xF0)
- #define ADAC_COEFF_A2 (0x0F)
- #define ADAC_DITH2 0x05
- #define ADAC_DSM0101 (1<<7) //DSM0101 mode
- #define ADAC_COEFF_A4 (0x0F)
- #define ADAC_OUT_CFG0 0x06
- #if defined(MT1389_REV_L) || defined(MT1389_REV_K)
- #define ADAC_CONFIG_1_0 0x00
- #define ADAC_CONFIG_1_1 0x01
- #define ADAC_CONFIG_1_2 0x02
- #define ADAC_CONFIG_1_3 0x03
- #define ADAC_CONFIG_1_4 0x04
- #define ADAC_CONFIG_1_5 0x05
- #define ADAC_CONFIG_1_6 0x06
- #define ADAC_CONFIG_1_7 0x07
- #define ADAC_CONFIG_1_8 0x08
- #define ADAC_CONFIG_1_9 0x09
- #define ADAC_CONFIG_1_A 0x0A
- #define ADAC_CONFIG_1_B 0x0B
- #define ADAC_CH1_AUPDN (1<<0)//GPIO
- #define ADAC_CH2_AUPDN (1<<1)//GPIO
- #define ADAC_CH1_AUDGAIN (1<<0)
- #define ADAC_CH2_AUDGAIN (1<<1)
- #define ADAC_ALL_CH_AUDGAIN 0x3F
- #define ADAC_CH1_AUCTLI (1<<0)
- #define ADAC_CH2_AUCTLI (1<<1)
- #define ADAC_ALL_CH_AUCTLI 0x3F
- #else
- #define ADAC_CH1_AUPDN (1<<0)
- #define ADAC_CH2_AUPDN (1<<1)
- #define ADAC_CH1_AUDGAIN (3<<2)
- #define ADAC_CH2_AUDGAIN (3<<4)
- #define ADAC_CH1_AUCTLI (1<<6)
- #define ADAC_CH2_AUCTLI (1<<7)
- #endif
- #define ADAC_OUT_CFG1 0x07
- #define LR_PU 0x3c
- #define LR_PD 0x03
- #define all_PU 0x00
- #define all_PD 0x3F
- #define ADAC_CH1_AUCTLO (1<<0)
- #define ADAC_CH2_AUCTLO (1<<1)
- #if defined(MT1389_REV_L) || defined(MT1389_REV_K)
- #define ADAC_ALL_CH_AUCTLO 0x3F
- #define ADAC_CH1_SETZERO (1<<0)
- #define ADAC_CH2_SETZERO (1<<1)
- #define ADAC_ALL_CH_SETZERO 0x3F
- #define ADAC_CH1_TMSETZERO (1<<0)
- #define ADAC_CH2_TMSETZERO (1<<1)
- #define ADAC_ALL_CH_TMSETZERO 0x3F
- #define ADAC_CH1_MODOEN (1<<0)
- #define ADAC_CH2_MODOEN (1<<1)
- #define ADAC_ALL_CH_MODOENO 0x3F
- #define ADAC_AL (1<<0)
- #define ADAC_AR (1<<1)
- #define ADAC_ALS (1<<2)
- #define ADAC_ARS (1<<3)
- #define ADAC_ALF (1<<4)
- #define ADAC_ARF (1<<5)
- #else
- #define ADAC_CH1_SETZERO (1<<2)
- #define ADAC_CH2_SETZERO (1<<3)
- #define ADAC_CH1_TMSETZERO (1<<4)
- #define ADAC_CH2_TMSETZERO (1<<5)
- #define ADAC_CH1_MODOEN (1<<6)
- #define ADAC_CH2_MODOEN (1<<7)
- #endif
- #define ADAC_OUT_CFG2 0x08
- #define ADAC_CH1_COFF (1<<0)//GPIO
- #define ADAC_CH2_COFF (1<<1)//GPIO
- #define ADAC_AUPS (0<<2)
- #define ADAC_EXT_CLK_EN (1<<5)
- #define ADAC_RESET (1<<6)// not finish
- #define ADAC_AUTEST 0x09
- #define ADAC_AUREV 0x0A
- #if defined(MT1389_REV_L) || defined(MT1389_REV_K)
- #define ADAC_AKIN2 0x0A
- #define ADAC_ADVCM 0x0B
- #define ADAC_AKIN1 0x0C
- #define AKIN1_EN (1<<2)//
- #define AKIN1_E2 (1<<4) //
- #endif
- #define APLL_CAL_CNTL 0x0D //APLL calibration[7:0]
- #define ADAC_MON 0x0E
- #define ADAC_MUTE_ALCK 0x29
- #define ADAC_ACLK_MUTE (0xE0)
- #if defined(MT1389_REV_L) || defined(MT1389_REV_K)
- #ifdef MTK_AUD_ADC
- #define AADC_CFG0 0x32
- #define OSR_SEL (3<<1)
- #define IADC_SEL (1<<0)
- #define AADC_CFG1 0x33
- #define ADC_ANALOG0 0x37 //AADC_CKDIV in 89E
- #define ADC_ANALOG1 0x38
- #define ADC_ANALOG2 0x39
- #define COMPTIMSEL (1<<6)
- #define ADC_ANALOG3 0x3a
- #define AAD_RST (1<<4)
- #define ADC_ANALOG4 0x3b
- #define CDSREN (1<<0)
- #define AUADCR_PD (1<<3)
- #define CDSENL (1<<4)
- #define AUADCL_PD (1<<7)
- #define AAD_TEST 0x3d
- #define AAD_TEST0 (1<<0)
- #endif
- #endif
- #elif (defined(MT1389_REV_HD)||defined(MT1389_REV_E))
- #define IO_AL (1<<5)
- #define IO_AR (1<<4)
- #define IO_ALS (1<<3)
- #define IO_ARS (1<<2)
- #define IO_ALF (1<<1)
- #define IO_ARF (1<<0)
- #ifdef MTK_AUD_ADC
- #define AAD_TEST 0x02
- #define AAD_TEST0 (1<<0)
- #endif
- #define AADC_CKDIV 0x03
- #define ADAC_CH1 0x04
- #define ADAC_CH2 0x05
- #define ADAC_CH3 0x06
- #define ADAC_CH4 0x07
- #define ADAC_CH5 0x08
- #define ADAC_CH6 0x09
- #define ADAC_COFF (1<<7)
- #define ADAC_TMSETZERO (1<<6)
- #define ADAC_SETZERO (1<<5)
- #define ADAC_AUCTLO (1<<4)
- #define ADAC_AUCTLI (1<<3)
- #define ADAC_AUPDN (1<<2)
- #define ADAC_AUDGAIN (3<<0)
- #define ADAC_MODOEN 0x0A
- #define ADAC_MODOEN6 (1<<5)
- #define ADAC_MODOEN5 (1<<4)
- #define ADAC_MODOEN4 (1<<3)
- #define ADAC_MODOEN3 (1<<2)
- #define ADAC_MODOEN2 (1<<1)
- #define ADAC_MODOEN1 (1<<0)
- #define ADAC_AUPS 0x0B
- #define ADAC_AUTEST 0x0C
- #define ADAC_RESET (1<<7)
- #define ADAC_LPF_DIV 0x0D
- #define ADAC_MOD_DIV 0x0E
- #define ADAC_MUTE_ALCK 0x29
- #define ADAC_ACLK_MUTE (0xE0)
- #ifdef MTK_AUD_ADC
- #define AADC_CFG0 0x32
- #define OSR_SEL (3<<1)
- #define IADC_SEL (1<<0)
- #define AUADC_LEFT 0x37
- #define AUADC_RIGHT 0x38
- #define CDSXEN (1<<1)
- #define AUADCX_PD (1<<0)
- #define AUADC_BIAS 0x39
- #define EXTCLK_EN (1<<4)
- #define COMPTIMSEL (1<<3)
- #define AUADPS (7<<0)
- #endif
- #define ADAC_CTRL0 0x3A
- #define ADAC_OSR (0x03<<6)
- #define ADAC_INV_MOD_OUT (1<<5)
- #define ADAC_INV_SCF_CLK (1<<4)
- #define ADAC_INV_MOD_CLK (1<<3)
- #define ADAC_INV_LPF_CLK (1<<2)
- #define ADAC_18BIT (1<<1)
- #define ADAC_MUTE (1<<0)
- #define ADAC_CTRL1 0x3B
- #define ADAC_ASD_PIN (1<<7)
- #define ADAC_DSM0101 (1<<2)
- #define ADAC_INV_LRCK (1<<0)
- #define ADAC_MOD_C0 0x3c
- #define ADAC_COEFF_A3 (0xF0)
- #define ADAC_COEFF_A2 (0x0F)
- #define ADAC_MOD_C1 0x3d
- #define ADAC_MOD_SEL (1<<7)
- #define ADAC_MOD_OUT_DELAY (0x70)
- #define ADAC_COEFF_A4 (0x0F)
- #elif defined(MT1389_REV_D)
- #define ADAC_ATOP0 0x39
- #define ADAC_TMSETZERO (1<<7)
- #define ADAC_SETZERO (1<<6)
- #define ADAC_AUCTLO (1<<5)
- #define ADAC_AUCTLI (1<<4)
- #define ADAC_TMAUPDN (1<<3)
- #define ADAC_AUPDN (1<<2)
- #define ADAC_AUDGAIN (3<<0)
- #define ADAC_ATOP1 0x3a
- #define ADAC_CTRL_SEL (1<<6)
- #define ADAC_EXTCLK_EN (1<<5)
- #define ADAC_MONITOR (1<<4)
- #define ADAC_AUTEST (0x0F)
- #define ADAC_CTRL0 0x3b
- #define ADAC_OSR (0x03<<6)
- #define ADAC_INV_MOD_OUT (1<<5)
- #define ADAC_INV_SCF_CLK (1<<4)
- #define ADAC_INV_MOD_CLK (1<<3)
- #define ADAC_INV_LPF_CLK (1<<2)
- #define ADAC_18BIT (1<<1)
- #define ADAC_MUTE (1<<0)
- #define ADAC_CTRL1 0x3b
- #define ADAC_CLOCK_MON (3<<2)
- #define ADAC_FUNC_TEST (1<<1)
- #define ADAC_INV_LRCK (1<<0)
- #define ADAC_MOD_C0 0x3c
- #define ADAC_COEFF_A3 (0xF0)
- #define ADAC_COEFF_A2 (0x0F)
- #define ADAC_MOD_C1 0x3d
- #define ADAC_SYNC_CLK (1<<7)
- #define ADAC_MOD_OUT_DELAY (0x70)
- #define ADAC_COEFF_A4 (0x0F)
- #define ADAC_CLK_SET1 0xF9
- #define ADAC_CLK_SET2 0xFA
- #endif //MT1389_REV_D
- #ifdef MT1389_REV_K
- #define ADAC_AKIN2 0x0A
- #define ADAC_ADVCM 0x0B
- #define ADAC_AKIN1 0x0C
- #endif
- //////////////////////////////////////////////////////
- // RISC registers definition
- // video register
- //#define RW_FMTCTL (0x10AC>>2)
- //#define RW_VDO_PTRY (0x0C00>>2)
- //#define RW_VDO_PTRC (0x0C04>>2)
- //#define RW_VDO_PICSIZE (0x0C0C>>2)
- //#define RW_VDO_CTRL (0x0C2C>>2)
- // your register defined here
- #define SRV_RDDVD_CMD 0x05
- #define VFMT_REG_OFST (0x1000 >> 2)
- #define RO_IRQST (VFMT_REG_OFST + 0x00)
- #define RW_IRQEN (VFMT_REG_OFST + (0x04 >> 2))
- #define WO_IRQCR (VFMT_REG_OFST + (0x08 >> 2))
- #define IRQ_IRCI 0x1
- #define IRQ_STAI (0x1 << 1)
- #define IRQ_OSDI (0x1 << 2)
- #define IRQ_VURI (0x1 << 3)
- #define IRQ_SURI (0x1 << 4)
- #define IRQ_OURI (0x1 << 5)
- #define IRQ_GI (0x1 << 6)
- #define IRQ_PI (0x1 << 7)
- #define IRQ_MCFI (0x1 << 8)
- #define IRQ_VLDI (0x1 << 9)
- #define IRQ_T0I (0x1 << 10)
- #define IRQ_T1I (0x1 << 11)
- #define IRQ_NSPAI (0x1 << 13) // RISC null space
- #define IRQ_WFLAI (0x1 << 14) // RISC write to Flash
- #define IRQ_DSPI (0x1 << 15)
- #define IRQ_RS232I (0x1 << 16)
- #define IRQ_VLDECI (0x1 << 17)
- #define RO_FIQST (VFMT_REG_OFST + (0x0C >> 2))
- #define RW_FIQEN (VFMT_REG_OFST + (0x10 >> 2))
- #define WO_FIQCR (VFMT_REG_OFST + (0x14 >> 2))
- #define FIQ_VSYNC (0x1 << 17)
- #define FIQ_GI IRQ_GI
- #define FIQ_PI IRQ_PI
- // ATAPI Command register to 8032
- #define RW_TRBM0 (VFMT_REG_OFST + (0x18 >> 2))
- #define RW_TRBM4 (VFMT_REG_OFST + (0x1C >> 2))
- #define RW_TRBM8 (VFMT_REG_OFST + (0x20 >> 2))
- #define IDE_BSY (0x1 << 24)
- #define IDE_SKEY 0xFF
- #define IDE_SCODE (0xFF << 8)
- #define IDE_SQ (0xFF << 16)
- // Share-Memory register to 8032
- #define RW_TRBMC (VFMT_REG_OFST + (0x24 >> 2))
- #define RW_SHAINFO RW_TRBMC
- #define ATAPI_COMPLETE 0x1
- // ATAPI Status from 8032
- #define RO_TRAS0 (VFMT_REG_OFST + (0x28 >> 2))
- // IR Command from 8032
- #define RO_TRAS4 (VFMT_REG_OFST + (0x2C >> 2))
- // OSD Command from 8032
- #define RO_TRAS8 (VFMT_REG_OFST + (0x30 >> 2))
- #define WC_AINT (VFMT_REG_OFST + (0x34 >> 2))
- #define ACMDI 0x1
- #define ASHAI (0x1 << 1)
- #define APOKI (0x1 << 2)
- #define RO_AINT (VFMT_REG_OFST + (0x34 >> 2))
- #define CMDBSY 0x1
- #define SHAIBSY (0x1 << 1)
- // Servo Pin
- #define DEC_BSIOEN 0x02
- #define DEC_BSIOUT 0x03
- #define DEC_BSIOIN 0x04
- #define IO_DQS1 (1 << 6)
- #define IO_DQS0 (1 << 5)
- #define IO_TDO (1 << 3)
- #define IO_TMS (1 << 2)
- #define IO_TDI (1 << 1)
- #define IO_TCK (1 << 0)
- #endif //_H_MT1389_
