VHDL/FPGA/Verilog

开发平台：

Windows_Unix

ex3.v：源码内容

							module ex3;
integer a,b;
parameter size=7;
initial
  begin
    a=2;
    b=1;
    repeat(size) begin
      #5 a=a+1;
      #5 b=b+1;
    end
  end
initial
  $monitor($time,"a=%d,b=%d",a,b);
endmodule
    

						