-
-
cores
... XST, all from ISE.
Directory Structure
===================
doc/ Documentation
isim/ Scripts for running the Xilinx ISIM simulator
rtl/ Verilog and VHDL source files for synthesis
tb/ Testbench source files for verification
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SSBCC
... high speed, low fabric utilization
- vendor-independent Verilog output with a VHDL package file
- simple Forth-like assembly ... architecture file to be unchanged between simulation and an FPGA
build.
Stack errors include underflow and overflow, malformed ...
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brainfuck-processor
... the code as
is, the SRAM would be included on the FPGA and could be
preloaded with your code if for some odd ... are available for anything
you might want.
* Why Verilog?
I started writing this in VHDL but there are
no working implementations out there ...
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fpgasm
FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
#THIS PROJECT HAS BEEN MOVED!
https://github.com/FPGAsm/FPGAsm
See [the wiki](https://github.com/stacksmith/ ...
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bpm-sw-old-backup
... Repository containing the Beam Position Monitor FPGA firmware and
software.
==============================================================================
Folder Hierarchy organization:
*
|
|-- hdl:
| | HDL (Verilog/VHDL) cores related to the BPM. ...
-
HDMI2USB-jahanzeb-firmware
... Ahmad](https://github.com/jahanzeb) using hand coded VHDL/Verilog and with
cores from [OpenCores](OpenCores.org) ...
## Prerequisites
* Xilinx WebPack 14.2 - Needed for building FPGA firmware.
* sdcc > ???? - Needed for building Cypress USB firmware.
...
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