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berlekamp_parallel.rar
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源码类别：

VHDL/FPGA/Verilog

开发平台：

VHDL

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资源说明：The Berlekamp multiplier [3] uses two basis representations, the polynomial basis for the multiplier and the dual basis for the multiplicand and the product. Because it is normal practice to input all data in the same basis, this means some basis transformation circuits will be required. Fortunately for m = (3, 4, 5, 6, 7, 9, 10) the basis conversion from the dual to the polynomial basis - and vice versa - is merely a reordering of the basis coefficients [38]. For the important case m = 8 - for example the error-correcting systems used in CDs, DAT and many other applications operate over GF(28) - this basis conversion requires a reordering and two additions of the basis coefficients (Appendix C). In practice therefore, two additional XOR gates are required. Even including the extra hardware for basis conversions, the Berlekamp multiplier is known to have the lowest hardware requirements of all available bit-serial multipliers [24].
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