-
-
hw2.zip
Using the VHDL Entry Method, design a logic circuit that behaves as a 2-bit adder ( X + Y + CinOrBin ) with carry-in when the control input SubAddn is ‘0’ and behaves as a 2-bit subtracter ( X – Y – CinOrBin ) with borrow-in when the control input ...
-
hw3.zip
... to clear the count to 0, and enable input to enable counting. For now, you may assume that the clock to the counter is a 1 Hz clock. For subsequent homework, you need to design a circuit that generates the 1 Hz clock signal from the 50 MHz system clock.
-
HCF4069UB.zip
HCF4069UB
The HCF4069UB is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
The HCF4069UB consists of six COS/MOS
inverter circuits. This device is intended for all
general purpose ...
-
osis.zip
大功率可控整流电路的故障诊断技术Power Controlled Rectifier Circuit Fault Diagnosis
-
-
-
-
Electronics-and-Circuit-Analysis-Using-MATLAB---J
The book can be used by students, professional engineers and technicians. The
first part of the book can be used as a primer to MATLAB. It will be useful to
all students and professionals who want a basic introduction to MATLAB.
Parts 2 and 3 are for ...
-
Serpar.rar
... is different from the parity generated inside the serial to parallel circuit. When parity error is detected, the serial to parallel circuit would be reset before its normal operation can be performed. This is the operation for serial to ...
-
-
Go To English Version 超过100万源码资源，1000万源码文件免费下载
