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ebook_verilog_fine_state_machine.zip
Designing a synchronous finite state machine (FSM) is a common task for a digital
logic engineer. This paper discusses a variety of issues regarding FSM design using
Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and
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APR7.zip
... to some specification.
Two classes of frequency-selective digital filters
are considered: infinite impulse response (IIR) and finite
impulse response (FIR) filters. The design process
consists of determining the coefficients of the IIR or FIR
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199mfi.zip
... to some specification.
Two classes of frequency-selective digital filters
are considered: infinite impulse response (IIR) and finite
impulse response (FIR) filters. The design process
consists of determining the coefficients of the IIR or FIR
...
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functions.rar
... Manifold to another. Discrete Functions are functions which can be represented using a finite number of values. Given the finite extent of computer memory, algorithms which compute a function that satisfies some special properties are computing a ...
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ID3.rar
... which heuristically leads to small trees. The examples are given in attribute-value representation. The set of possible classes is finite. Only tests, that split the set of instances of the underlying example languages depending on the value of a single ...
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An_Dfa.rar
this code define the deterministic finite automata using genetic programming
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An_NFA1.rar
this code define non-deterministic finite automata using lisp
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