English
An Efficient Multi-Core SIMD Implementation for H.264AVC Encoder.
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1896k
资源说明：The optimization process of a H.264/AVC encoder on three different architectures is presented. The architectures are multi-
and singlecore and SIMD instruction sets have different vector registers size. The need of code optimization is fundamental
when addressing HD resolutions with real-time constraints. The encoder is subdivided in functional modules in order to better
understand where the optimization is a key factor and to evaluate in details the performance improvement. Common issues in both
partitioning a video encoder into parallel architectures and SIMD optimization are described, and author solutions are presented
for all the architectures. Besides showing efficient video encoder implementations, one of the main purposes of this paper is to
discuss how the characteristics of different architectures and different set of SIMD instructions can impact on the target application
performance. Results about the achieved speedup are provided in order to compare the different implementations and evaluate
the more suitable solutions for present and next generation video-coding algorithms.
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